Jäger ADwin-Pro, System And Hardware Description

Page: 117 / 218

ADwin-Pro Hardware, manual version 2.9, June 2006
113
Pro I: Digital-I/O- and Counter Modules
Pro-CNT-16/16 Rev. A
ADwin
Fig. 213 – Pro-CNT-16/16 Rev. A : Board and front panel
Counter 16 up counters
Counter resolution 16 bit
Input clock rate 10MHz max.
Signal pulse width min. 50ns
Inputs TTL
Trigger Input pos. TTL
Pull down resistor 10k
Ω
V
IH
min. 2.4V
V
IL
max. 0.8V
I
IH
max. 1mA
I
IL
max. 0.2mA
Voltage range, absolute -0.3V … 7V
Connector 37-pin DSub socket
Isolation No (see page 114 )
Fig. 214 – Pro-CNT-16/16 Rev. A : Specification
19CNT01
ON
1 2 3 4 5 6 7 8
A0 A1 A2 A3 A4 A5 A6 A7
FPGA FPGA
A
B
T
16245
LS19
LS19
LS19
LS19
LS19
LS19
LS19
OCX
FPGA FPGA
FP
G
A
CNT-16/16
COUNTER
INPUT