Jäger ADwin-Pro, System And Hardware Description

Page: 109 / 218

ADwin-Pro Hardware, manual version 2.9, June 2006
105
Pro I: Digital-I/O- and Counter Modules
Pro-CNT-VR4 (-L) Rev. A
ADwin
Fig. 195 – Pro-CNT-VR4 (-L) Rev. A : Board and front panel
Fig. 193 – Pro-CNT-VR4 Rev. A: Pin
assignment
Fig. 194 – Pro-CNT-VR4-L Rev. A:
Pin assignment
Counter 4 up/down counters
Counter resolution 32 bit
Input clock rate edge evaluation 1.25MHz max. per channel A,B
clock, direction 10MHz max.
S i g n a l p u l s e
width edge evaluation min. 800ns per channel A,B
clock, direction min. 50ns
Inputs TTL
Trigger Input pos. TTL
Pull down resistor 10k
Ω
V
IH
min. 2.4V
V
IL
max. 0.8V
I
IH
max. 0.55mA
I
IL
max. 0.01mA
Voltage range, absolute -0.3V … 7V
Connector 37-pin DSub socket
Isolation No (see page 106 )
Fig. 196 – Pro-CNT-VR4 (-L) Rev. A : Specification
CNTR 1 DIR
CNTR 1 B
CNTR 2 DIR
CNTR 2 B
CNTR 3 DIR
CNTR 3 B
CNTR 4 DIR
CNTR 4 B
DGND
EVENT IN
CNTR 1 CLR
CNTR 1 CLK
CNTR 1 A
RESERVED
CNTR 2 CLR
CNTR 2 CLK
CNTR 2 A
RESERVED
CNTR 3 CLR
CNTR 3 CLK
CNTR 3 A
RESERVED
CNTR 4 CLR
CNTR 4 CLK
CNTR 4 A
RESERVED
DGND
+5V, <100mA (unfused)
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CNTR 1 B
CNTR 2 B
CNTR 3 B
CNTR 4 B
DGND
EVENT IN
CNTR 1 LATCH
RESERVED
CNTR 1 A
RESERVED
CNTR 2 LATCH
RESERVED
CNTR 2 A
RESERVED
CNTR 3 LATCH
RESERVED
CNTR 3 A
RESERVED
CNTR 4 LATCH
RESERVED
CNTR 4 A
RESERVED
DGND
+5V, <100mA (unfused)
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
RESERVED
RESERVED
RESERVED
RESERVED
19CNT01
ON
1 2 3 4 5 6 7 8
A0 A1 A2 A3 A4 A5 A6 A7
FPGA FPGA
A
B
T
16245
LS19
LS19
LS19
LS19
LS19
LS19
LS19
OCX
FPGA FPGA
FP
G
A
CNT-VR4
COUNTER
INPUT
CNT-VR4-L
COUNTER
INPUT