iWave iW-RainboW-G20M, Hardware User'S Manual

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REL1.3
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RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.8.4 Data UART Interface
The RZ/G1M/G1N Qseven SOM supports two Data UART interface on Expansion connector2 along with one more on
Qseven Edge connector and one on Expansion connector1. RZ/G1M/G1N CPU’s SCIF1 & HSCIF1 controller is used for
Data UART interface with Transmit & Receive signal on Expansion connector2.
The RZ/G1M/G1N CPU’s SCIF module has two 16-stage FIFO buffers separately for transmission and reception, which
enables fast, efficient, and uninterrupted full duplex communication. It has On-chip baud rate generator that allows
any bit rate to be selected. Also it supports DMA transfers.
The RZ/G1M/G1N CPU’s HSCIF1 is a high speed serial communication interface with built-in FIFO buffers that handles
asynchronous communication. It has two 128-stageFIFO buffers separately for transmission and reception, which
enables fast, efficient, and uninterrupted communication.
For more details, refer Expansion connector2 pins 77 & 79 for SCIF1 and 62, 63, 64, 65 & 67 for HSCIF1 on Table 7.
Note: In RZ/G1M/G1N CPU, MSIOF1 and HSCIF1 are multiplexed in same pins and so MSIOF1 cannot be supported
when HSCIF1 is supported with Hardware flow control signals. If HSCIF1is supported without Hardware flow control
signals, then MSIOF1 also can be supported.
2.8.5 PWM Interface
The RZ/G1M/G1N Qseven SOM supports one PWM interface on Expansion Connector2. RZ/G1M/G1N CPU’s PWM 1
channel is used for PWM interface. This PWM timer has a 10-bit counter and supports configurable PWM output cycle
within the range from 2 cycles to 224 × 1024 cycles of internal bus clock (i.e. from 30.77 ns to 264 seconds when bus
clock = 65 MHz). Also it supports continuous pulse output mode or single pulse output mode.
For more details, refer Expansion connector2 pin 60 on Table 7.
2.8.6 Memory Bus Interface
The RZ/G1M/G1N Qseven SOM supports 16bit Memory Bus interface on Expansion Connector2. RZ/G1M/G1N CPU’s
LBSC module is used for memory bus interface.
The RZ/G1M/G1N CPU’s LBSC module performs bus arbitration and necessary interface conversion for the accesses
from the CPU and DMA accesses from LBSC-DMAC channels 0 to 2 and outputs them to the external buses. LBSC
configuration allows diversity in methodology for accessing various external devices that are assigned to their
corresponding areas. The LBSC outputs bus signals are in synchronization with the external bus clock and frequency of
the external bus clock CLKOUT signal is 65.0 MHz.
For more details, refer Expansion connector2 pins 1 to 40, 42, 44, 46, 47, 49, 51, 53, 55, 57 & 61 on Table 7.