REL 1.0
Page 33 of 89
RZ/G1M/G1N Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table 4: Board Configuration Switch
SW2
Bits
SW2
Bit Name
Description
OFF
ON
1
BIOS_DSIABLE# -
-
2
BATLOW#
-
-
3
LID_BTN#
-
-
4
USB_SELECT
-
-
5
CODEC_SELECT -
-
6
PCIe_SELECT
PCIe channel0 is connected to Mini-PCIe Slot
.
PCIe channel0 is connected to PCIex4 Slot.
7
DEBUG_SELECT -
Debug Port is selected as UART.
8
USB_ID
USB0 acts as Host mode or Device mode
based on the connected cable in USB MicroAB
connector (J2).
USB0 is forced to Host Mode.
2.4.3
Reset Switch
The RZ/G1M/G1N Qseven carrier board supports Push button switch (SW4) to reset the RZ/G1M/G1N CPU.
“RSTBTN” signal of Qseven MXM connector is directly connected from Reset Push button switch. This Reset Push
button switch (SW4) is physically located at the top of the board as shown below.
Figure 5: Reset Switch