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REL 1.0
Page 26 of 89
RZ/G1M/G1N Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven MXM
Connector Pin
Name
Signal Name
Signal Type/
Termination
Description
158
PCIE_RST#
GPIO_PCIe_RST(GP7
_19)
I, 3.3V CMOS
PCIe reset.
This pin is connected to PCIe x 4 connector
(J4) and Mini PCIe connector (J26).
159
GND
GND
Power
Ground.
160
GND
GND
Power
Ground.
161
P
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
162
P
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
163
PCIE3_TX-
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
164
PCIE3_RX-
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
165
GND
GND
Power
Ground.
166
GND
GND
Power
Ground.
167
P
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
168
P
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
169
PCIE2_TX-
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
170
PCIE2_RX-
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.
171
UART0_TX
SCIFB1_TXD(GP7_12) I, 3.3V CMOS
SCIFB1 interface serial data transmitter.
This pin is connected to Data UART Header
(J1) 05
th
Pin.
172
UART0_RTS#
SCIFB1_RTS#(GP7_9) I, 3.3V CMOS
SCIFB1
interface
ready
to
receive
handshake signal.
This pin is connected to Data UART Header
(J1) 06
th
Pin.
173
P
NA
-
NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to PCIex4 connector
(J4) in carrier board.