iWave iW-RainboW-G20D, Hardware User'S Manual, Page: 22 / 89

REL 1.0
Page 22 of 89
RZ/G1M/G1N Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven MXM
Connector Pin
Name
Signal Name
Signal Type/
Termination
Description
99 e/
DU0_LVDS_CH0_P IO, DIFF LVDS primary channel differential pair0
positive.
This pin is connected to LVDS Receiver.
100 e/
NA - NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
101 eDP0_TX0-/
LVDS_A0- DU0_LVDS_CH0_N IO, DIFF LVDS primary channel differential pair0
negative.
This pin is connected to LVDS Receiver.
102 eDP1_TX0-/
LVDS_B0- NA - NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
103 e/
DU0_LVDS_CH1_P IO, DIFF LVDS primary channel differential pair1
positive.
This pin is connected to LVDS Receiver.
104 e/
NA - NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
105 eDP0_TX1-/
LVDS_A1- DU0_LVDS_CH1_N IO, DIFF LVDS primary channel differential pair1
negative.
This pin is connected to LVDS Receiver.
106 eDP1_TX1-/
LVDS_B1- NA - NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
107 e/
DU0_LVDS_CH2_P IO, DIFF LVDS primary channel differential pair2
positive.
This pin is connected to LVDS Receiver.
108 e/
NC - NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
109 eDP0_TX2-/
LVDS_A2- DU0_LVDS_CH2_N IO, DIFF LVDS primary channel differential pair2
negative.
This pin is connected to LVDS Receiver.
110 eDP1_TX2-/
LVDS_B2- NA - NC in RZ/G1M/G1N Qseven SOM.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
111 LVDS_PPEN GPIO_LVDS_PPEN(G
P7_25) I, 3.3V CMOS/
10K PU LCD Panel Power Enable.
112 LVDS_BLEN GPIO_LVDS_BLEN(GP
5_14) I, 3.3V CMOS/
10K PU LCD Panel Backlight Enable Control.