REL0.2
Page 38 of 88
Zynq Ult MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.8
Additional Features
2.8.1
Clock Synthesizers
The Zynq Ult MPSoC SBC supports 6-
output Clock Synthesizer “SI5332A
-D-
GM1” for on board clock
distribution. This Clock Generator outputs are connected to PS-GTR, PL-GTH Transceiver Banks Reference Clock on
Zynq Ult MPSoC through 0.01uF AC coupling capacitors. An external 25MHz crystal is connected to this Clock
Synthesizer
for reference. This Clock Synthesizer
supports from 5 MHz to 333.33 MHz clock output and configurable
through PS I2C0.
Table 7: Clock Synthesier Output Clocks
Pin
No
Pin Name
Signal Name
Programmed
Frequency
Connected To
12
OUT0
PS_MGTREFCLK0P_505
135MHz
Zynq US+ MPSoC-U12.F23.
11
OUT0b
PS_MGTREFCLK0N_505
Zynq US+ MPSoC-U12.F24.
15
OUT1
PS_MGTREFCLK2P_505
100 MHz
Zynq US+ MPSoC-U12.C21.
14
OUT1b
PS_MGTREFCLK2N_505
Zynq US+ MPSoC-U12.C22.
19
OUT2
GTREFCLK0P_224
148.5 MHz
Zynq US+ MPSoC-U12.Y6.
18
OUT2b
GTREFCLK0N_224
Zynq US+ MPSoC-U12.Y5.
22
OUT3
GTREFCLK1P_224
148.5 MHz
Zynq US+ MPSoC-U12.V6.
21
OUT3b
GTREFCLK1N_224
Zynq US+ MPSoC-U12.V5.
27
OUT4
PS_MGTREFCLK3P_505
125 MHz
Zynq US+ MPSoC-U12.A21.
26
OUT4b
PS_MGTREFCLK3N_505
Zynq US+ MPSoC-U12.A22.
31
OUT5
NA
-
NC.
30
OUT5b
NA
NC.
Important Note: In Zynq Ult MPSoC SBC, OUT3 & 3b from clock synthesizer is optionally connected to
GTREFCLK1P & N_224 of Zynq Ult MPSoC V6 & V5 . By default GTREFCLK1P & N_224 of V6 & V5 is connected
from HDMI IN Connector(J9).
2.8.2
JTAG Header
The Zynq Ult MPSoC SBC supports 14Pin JTAG Header (J3) for JTAG interface. JTAG Interface Signals from
MPSoC’s PS BANK503
is connected to this Header through 1.8V to 3.3V level translator.
The Zynq Ult MPSoC’s
PS and PL share a common set of JTAG pins and each have their own TAP controller which are chained together inside
the Zynq Ultrascale MPSoC. These JTAG interface signals are at 3.3V Voltage level.
The JTAG Header (J3) is physically located on topside of the SBC as shown below. JTAG-HS2 Programming Cable can
be directly connected to this JTAG Header.
