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Zynq Ult MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6
Features from PS-GTR
The Zynq Ult MPSoC supports four Multi-Gigabit PS-GTR transceivers with data rate from 1.25Gbps to 6.0Gbps.
This PS-GTR transceiver lanes provide I/O path for MPSoC MAC controllers and their link partner outside.
The Zynq Ult MPSoC SBC supports two PS GTR transceivers (Lane0 & Lane1) for Display Port Connector, one
PS GTR transceiver (Lane2) for USB3.0 interface and another one PS GTR transceiver (Lane3) for SATA on M.2
Connector.
•
2 lanes of DisplayPort (TX only) at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s
•
1 lane of USB3.0 channels at 5.0Gb/s
•
1 lane of SATA channels at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s
2.6.1
Display Port Connector
The Zynq Ult MPSoC SBC supports Display port connector through PS-GTR Lanes of Zynq Ult MPSoC
PS. PS-GTR Lane0 & Lane1 from Zynq Ult MPSoC PS is connected to Display port connector to support dual
lane display port. The Zynq Ult MPSoC can support upto 4K@30 resolution.
The Display port connector supports AUX+ & AUX- signals from the PL Bank IOs. Also it supports Hot plug detect signal
and connected to PL Bank IO. This Display Port connector (J5) is physically located at the top of the board as shown
below.
Figure 8: Display Port Connector
