REL 1.2
Page 52 of 82
i.MX6 Qseven PMIC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.9.1
Parallel Camera Interface2
i.MX6 Qseven PMIC SOM supports one camera interface along with MIPI CSI interface on Expansion connector2 and
one more camera interface on Expansion connector1. i.MX6 QuadPlus/Quad/DualPlus/Dual CPU has two IPU block
and each IPU has two input ports CSI0 and CSI1 which can receive data concurrently and independently. At any given
time, an IPU input port may receive data either from a parallel external port or from the MIPI/CSI-2 receiver.
i.MX6 IPU’s CSI1 parallel port is used for camera2 interface which provides direct connectivity to most relevant
image sensors and to TV decoders. The sensor is the master of the pixel clock (PIXCLK) & synchronization signals
where synchronization signals can be received using dedicated control signals method (HSYNC & VSYNC) or controls
embedded in data stream method (BT.656 protocol). i.MX6 Qseven PMIC SOM supports 8bit camera interface.
For more details, refer Expansion connector2 pins 48 to 58 on
Note: i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU.
2.9.2
MIPI CSI Interface
i.MX6 Qseven PMIC SOM supports four data lane MIPI CSI interface (excluding clock lane) from 80 Mbps up to 1
Gbps speed per data lane on Expansion connector2. i.MX6 QuadPlus/Quad/DualPlus/Dual CPU has two IPU block
and each IPU has two input ports CSI0 and CSI1 which can receive data concurrently and independently. At any given
time, an IPU input port may receive data either from a parallel external port or from the MIPI/CSI-2 receiver.
The MIPI/CSI-2 port can receive up to 4 concurrent data channels. Each data channel is routed to a different CSI
input of the IPU (2 IPUs, 2 CSIs on each IPU; a total of 4 CSI inputs). Pixel data can be further processed by the IPU.
Other data types can be transferred through a CSI transparently as generic data to the system memory.
i.MX6 CPU’s IPU with MIPI CSI-2 Host controller & MIPI D-PHY is used for MIPI CSI interface. It is compliant with MIPI
Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.00 and Interface with MIPI D-PHY following PHY
Protocol Interface (PPI) as defined in MIPI Alliance Specification for D-PHY Version 1.00. It supports all primary and
secondary data formats with RGB, YUV and RAW colour space definitions from 24-bit down to 6-bit per pixel.
For more details, refer Expansion connector2 pins 61,63,65,67,69,71,73.75,79 & 80 on
Note: i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU and so only two MIPI CSI data lane is supported.
