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Zynq Ult MPSoC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.3.2
MPSoC Reset
The Zynq Ult MPSoC SOM
uses PMIC’s Reset output (
nRESET) for PS Power On Reset and connected to
PS_POR_B pin of MPSoC. Also it supports warm reset input from Board to Board Connector2 pin35 and connected to
PS_SRST_B pin of MPSoC.
2.3.3
MPSoC Reference Clock
The Zynq Ult MPSoC SOM supports on board clock oscillators for reference clock to different blocks of Zynq
Ult MPSoC. These reference clock details are mentioned in the below table.
Table 3: Zynq Ult MPSoC SOM Reference Clock.
Sl.
No
On-SOM Oscillator
Frequency
SoC Ball Name/
Pin Number
Signal Type/
Termination
Description
1
33.33MHz
PS_REF_CLK/P19
1.8V, LVCMOS
33.33Mhz single ended reference
clock for PS.
2
100MHz
¹
IO_L5P_HDGC_45/G16
1.8V², LVCMOS
100Mhz single ended reference
clock for PL. This is connected to
PL Bank45 HDGC Global clock pin.
3
300MHz
IO_L11P_T1U_N8_GC_65/AG8 &
IO_L11N_T1U_N9_GC_65/AH8
1.8V, LVDS
LVDS reference clock for PL DDR4.
This is connected to PL Bank65
Global clock pins.
¹ Important Note: I/O voltage of PL Bank45 is software configurable. Since this oscillator supports 1.8V to 3.3V VCC
only, this reference clock can be used only if the I/O voltage of PL Bank45 is set between 1.8V to 3.3V.
²
Mentioned voltage level is based on default I/O voltage set to PL Bank45.
