iWave Hardware User Guide, Hardware User'S Manual

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REL1.0
Page 16 of 80
Zynq Ult MPSoC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Peripheral
Interface
MIO EMIO
Quad-SPI
NAND Yes No
USB2.0: 0,1 Yes: External PHY No
SDIO 0,1 Yes Yes
SPI: 0,1
I2C: 0,1
CAN: 0,1
GPIO Yes
CAN: External PHY
GPIO: Up to 78 bits Yes
CAN: External PHY
GPIO: Up to 96 bits
GigE: 0,1,2,3 RGMII v2.0:
External PHY Supports GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII, and
1000BASE-X in Programmable Logic
UART: 0,1 Simple UART:
Only two pins (TX and RX) Full UART (TX, RX, DTR, DCD, DSR, RI, RTS, and CTS) requires either:
• Two Processing System (PS) pins (RX and TX) through MIO and six
additional Programmable Logic (PL) pins, or
• Eight Programmable Logic (PL) pins
Debug Trace
Ports Yes: Up to 16 trace bits Yes: Up to 32 trace bits
Processor JTAG Yes Yes
The Zynq Ult MPSoC’s P L Banks are classified as high-performance (HP) banks or high-density (HD) banks.
The HP Bank I/Os are optimized for highest performance operation organized in banks of 52pins. The HD Bank I/Os
are reduced-feature I/Os organized in banks of 24pins.
In Zynq Ult MPSoC PL, each bank supports four global clock (GC or HDGC) input pin pairs. GC pins have direct
access to the global clock buffers, MMCMs and PLLs of the same Bank. HDGC pins are from HD I/O banks and have
direct access only to the global clock buffers.
Also Zynq Ult MPSoC supports two types of high speed transceivers namely GTH and PS-GTR. These
transceivers are arranged in groups of four known as a transceiver Quad. GTH transceivers are from PL and PS-GTR
transceivers are from PS.
2.3.1 MPSoC Power
The Zynq Ult MPSoC SOM uses discrete power regulators along with DA9062 PMIC from Dialog
Semiconductor for MPSoC power management. In SOM, PS low-power domain, PS full-power domain & PL power
domain supply voltage (VCC_PSINTLP, VCC_PSINTFP, VCCINT) is fixed to 0.85V or 0.9V based on the speed grade of
the MPSoC. Also all PS Bank (VCCO_PSIO) I/O voltage is fixed to 1.8V.
The I/O voltage of PL HP Banks (PL Bank 64 & 66) which are connected to Board to Board Connectors is fixed to 1.8V.
The I/O voltage of PL HD Banks (PL Bank 45 & 46) which are connected to Board to Board Connectors are generated
from PMIC LDO3 and by default set to 1.8V. I/O voltage is configurable through software after bootup.