3.6.3. Single channel Inhibit
INFORMATION
INFORMATION
INHIBIT is an external signal, that switches off the high voltage for the device or a specific channel.
The Sub-D connector on the bottom of the front panel allows to install an Inhibit for each channel. The pin assignment is
as follows:
Channel 0 – 3 / GND
0
1
2
3
GND
SUB-D9 connector pin
1
2
3
4
5
6
7
8
9
Table 6: INHIBIT connector pinout
The INHIBIT signals are TTL-level, the signal logic is defined by selected option. The following configurations are possible:
Option 1 – IU (default)
INHIBIT signal logic:
LOW-active (LOW
➜
HV-generation stopped)
default state:
HIGH (internal pull-up resistor applied)
open INHIBIT signal input:
HV enabled
Option 2 – ID
INHIBIT signal logic:
LOW-active (LOW
➜
HV-generation stopped)
default state:
LOW (internal pull-down resistor applied)
open INHIBIT signal input:
HV disabled
Option 3 – NIU
INHIBIT signal logic:
HIGH-active (HIGH
➜
HV-generation stopped)
default state:
HIGH (internal pull-up resistor applied)
open INHIBIT signal input:
HV disabled
Option 4 – NID
INHIBIT signal logic:
HIGH-active (HIGH
➜
HV-generation stopped)
default state:
LOW (internal pull-down resistor applied)
open INHIBIT signal input:
HV enabled
The INHIBIT signal must be applied for at least 100 ms to guarantee a detection. If an Inhibit signal is detected, the
channel status bit “
isExternalInhibit
” and the channel event status bit “
EExternalInhibit”
are set. One of the following
reactions to this signal can be programmed (see chapter “
6.5.1.7 External channel inhibit
” in the
CAN_EDCP_Programmers-Guide.pdf)
•
No Action (default)
•
Turn off the channel with ramp
•
Shut down the channel without ramp
•
Shut down all channels without ramp
When the INHIBIT is no longer active, the Inhibit flag must be reset before the voltage can be switched on again.
NHR – NIM standard High Voltage Power Supply | Last changed on: 25.11.2019 |
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