iPECS-LIK
Feature Description & Operation Manual
Issue 6.0d1
148
2.61 REDUNDANT SYSTEM PROCESSOR
Description
The iPECS system supports redundant processor operation. The redundant system processor
is a hot standby processor. The LAN2 port of the master MFIM is connected directly to the
LAN2 port of the standby MFIM. The standby MFIM monitors the active MFIM and takes over
system control if the:
active MFIM power fails.
active MFIM is reset.
LAN1 connection to the active MFIM fails or is removed.
standby MFIM does not receive a polling message from the active MFIM for
1 minute.
If failure occurs, the standby MFIM will take over and maintain control of the system. When the
original master recovers from failure, it functions in the standby processor mode. The active
MFIM will maintain the system database for both the active and standby processor.
Operation
Operation of redundant processors is automatic when installed.
Conditions
1. The Master/Slave switch on the main MFIM must be set in the Master position and
the backup MFIM must be set in the Slave position to match the system Admin
settings.
2. All eight wires of the Cat 5 cable must be terminated on the RJ45 connectors.
3. It is not possible to use the VSF(Internal VM) and a VMIM(external or commercial
VM) should be installed for CPU redundancy. If you set redundancy ON by 161-
Btn 20,
VSF goes to “OUT of Service”.
4. Master and Slave can be active in case LAN2 cable is out of order or other reason.
These dual active can be protected using IP watch timer(181-B14). If you set the
timer as 1 sec, Master send ARP to Slave every one second and Slave can detect
Master alive. In this case, Slave can disable LAN1 for protect dual active.
Programming
NUMBERING PLAN
1 LAN2 Master IP Address (PGM 102-Btn 16)
2 LAN2 Slave Address (PGM 102-Btn 17)
SYSTEM
1 CPU Redundancy (PGM 161-Btn 20)
2 Change Active MFIM by Power Fail (PGM 161-Btn
21)
3 IP WATCH timer (PGM 181-Btn 14)
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