Inventec P47 series, Service Manual

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K800G4 BMC Specification
5
BMC would check those statuses at BMC runtime, while initial/write/delete/read SDR/SEL failed, the error bit would be set
accordingly and user can retrieve the status by “Get Self Test Results Command”. BIOS would issue the ‘Get Self Test Results
Command’ to get the BMC self-test results every time system power up(the result will show on BIOS setup menu), if the
SEL-test failed, BMC would create a SEL for self-test failure, the error code (Get Self Test Results Command Response data
Byte 2
、
3). The event would not be stored in SEL because of SEL function abnormally.
Behavior Byte Data Filed
Request 1 Completion Code-
Response
1
55h = No error. All Self Tests Passed.
56h = Self Test function not implemented in this controller.
57h = Corrupted or inaccessible data or devices
58h = Fatal hardware error (system should consider BMC inoperative). This will indicate
that the controller hardware (including associated devices such as sensor
hardware or RAM) may need to be repaired or replaced.
FFh = reserved.
all other: Device-specific ‘internal’ failure. Refer to the particular device’s specification
for definition.
2
For byte 2 = 55h, 56h, FFh: 00h
For byte 2 = 58h, all other: Device-specific
For byte 2 = 57h: self-test error bit field. Note: returning 57h does not imply that all
tests were run, just that a given test has failed. I.e. 1b means ‘failed’, 0b
means ‘unknown’.
[7] 1b = Cannot access SEL device
[6] 1b = Cannot access SDR Repository
[5] 1b = Cannot access BMC FRU device
[4] 1b = IPMB signal lines do not respond
[3] 1b = SDR Repository empty
[2] 1b = Internal Use Area of BMC FRU corrupted
[1] 1b = controller update ‘boot block’ firmware corrupted
[0] 1b = controller operational firmware corrupted
3.
BMC Watchdog
A watchdog timer (WDT) is a device that performs a specific operation after a certain period of time if something goes
wrong with an electronic system and the system does not recover on its own. And both hardware WDT and IPMI standard
WDT was implemented on this platform.
3.1 IPMI Standard Watchdog
The BMC implement the SMS ‘OS watchdog’ & BIOS FRB2 watchdog timers in order to allow host software check pointing
and system recovery on a timeout. The watchdog timer would be disabled by default. Beside system recovery on timeout,
it also supports a pre-timeout interrupt using the KCS non-communication messaging interrupt (SMS_ATN flag).
3.2 Automatic System Recovery
The BMC supports the watchdog related command defined in IPMI v2.0 Spec for BIOS/SMS. The SMS /BIOS can use these
timer functions to support the automatic system recovery function. Note that one who acquired and activated the
watchdog timer is responsible to reset the timer countdown. If the pre-defined interval expired, the configured timer
actions will be executed. Also, the event of watchdog timeout will be logged into SEL for later examination. The timeout
action list as below:

Hard Reset

Power Down

Power Cycle