Reference Number: 327043-001
49
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
Note:
The address comparison always ignores the lower 12 bits of the physical address, even
if they system is interleaving between sockets at the cache-line level. Therefore, this
mask will always match to an OS virtual page, even if only a fraction of that page is
mapped to the Home Agent under investigation. The mask is not adjusted for large
pages, so matches will only be allowed within 4K granularity.
2.4.4
HA Performance Monitoring Events
The performance monitoring events within the HA include all events internal to the HA as well as
events which track ring related activity at the HA ring stops. Internal events include the ability to
track Directory Activity, Direct2Core Activity, iMC Read/Write Traffic, time spent dealing with Conflicts,
etc.
Other notable event types:
• iMC RPQ/WPQ Events
Determine cycles the HA is stuck without credits in to the iMCs read/write queues.
• Ring Stop Events
To track Egress and ring utilization (broken down by direction and ring type) statistics, as well as
ring credits between the HA and Intel® QPI.
• Local/Remote Filtering
A number of HA events is extended to support filtering the origination from a local or remote
caching agent .
• Snoop Latency
2.4.4.1
On the Major HA Structures:
The 128-entry
TF
(Tracker File) holds all transactions that arrive in the HA from the time they arrive
until they are completed and leave the HA. Transactions could stay in this structure much longer than
they are needed. TF is the critical resource each transaction needs before being sent to the iMC
(memory controller)
TF average occupancy == (valid cnt * 128 / cycles)
TF average latency == (valid cnt * 128 / inserts)
Other Internal HA Queues of Interest:
TxR (aka EGR)
- The HA has Egress (responses) queues for each ring (AD, AK, BL) as well as queues
to track credits the HA has to push traffic onto those rings.
Table 2-39. HA_PCI_PMON_BOX_ADDRMATCH0 Register – Field Definitions
Field
Bits
HW
Reset
Val
HW
Reset
Val
Description
lo_addr
31:6
RWS
0 Match to this System Address - Least Significant 26b of cache
aligned address [31:6]
rsv
5:0
RV
0 Reserved (?)
