Reference Number: 327043-001
19
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
2.2
UBox Performance Monitoring
2.2.1
Overview of the UBox
The UBox serves as the system configuration controller for the Intel Xeon Processor E5-2600 family
uncore.
In this capacity, the UBox acts as the central unit for a variety of functions:
• The master for reading and writing physically distributed registers across the uncore using the
Message Channel.
• The UBox is the intermediary for interrupt traffic, receiving interrupts from the sytem and
dispatching interrupts to the appropriate core.
• The UBox serves as the system lock master used when quiescing the platform (e.g., Intel® QPI
bus lock).
2.2.2
UBox Performance Monitoring Overview
The UBox supports event monitoring through two programmable 44-bit wide counters
(U_MSR_PMON_CTR{1:0}), and a 48-bit fixed counter which increments each u-clock. Each of these
counters can be programmed (U_MSR_PMON_CTL{1:0}) to monitor any UBox event.
For information on how to setup a monitoring session, refer to
Section 2.1, “Uncore Per-Socket
Performance Monitoring Control”
.
2.2.3
UBox Performance Monitors
2.2.3.1
UBox Box Level PMON State
The following registers represent the state governing all box-level PMUs in the UBox.
U
Table 2-1.
UBox Performance Monitoring MSRs
MSR Name
MSR
Address
Size
(bits)
Description
U_MSR_PMON_CTR1
0x0C17
64 U-Box PMON Counter 1
U_MSR_PMON_CTR0
0x0C16
64 U-Box PMON Counter 0
U_MSR_PMON_CTL1
0x0C11
64 U-Box PMON Control for Counter 1
U_MSR_PMON_CTL0
0x0C10
32 U-Box PMON Control for Counter 0
U_MSR_PMON_UCLK_FIXED_CTR
0x0C09
64 U-Box PMON UCLK Fixed Counter
U_MSR_PMON_UCLK_FIXED_CTL
0x0C08
32 U-Box PMON UCLK Fixed Counter Control
