Intel® Xeon® Processor 5600 Series
27
Specification Update, March 2010
BD32.
xAPIC Timer May Decrement Too Quickly Following an Automatic
Reload While in Periodic Mode
Problem:
When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Implication:
When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD33.
Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Problem:
Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor
uses to access the VMCS and data structures referenced by pointers in the VMCS. Due
to this erratum, a VMX access to the VMCS or referenced data structures will instead
use the memory type that the MTRRs (memory-type range registers) specify for the
physical address of the access.
Implication:
Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory type
will be used but the processor may use a different memory type.
Workaround:
Software should ensure that the VMCS and referenced data structures are located at
physical addresses that are mapped to WB memory type by the MTRRs.
Status:
For the steppings affected, see the
BD34.
B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
Problem:
Some of the B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may be
incorrectly set for non-enabled breakpoints when the following sequence happens:
1. MOV or POP instruction to SS (Stack Segment) selector;
2. Next instruction is FP (Floating Point) that gets FP assist
3. Another instruction after the FP instruction completes successfully
4. A breakpoint occurs due to either a data breakpoint on the preceding instruction or
a code breakpoint on the next instruction.
Due to this erratum a non-enabled breakpoint triggered on step 1 or step 2 may be
reported in B0-B3 after the breakpoint occurs in step 4.
Implication:
Due to this erratum, B0-B3 bits in DR6 may be incorrectly set for non-enabled
breakpoints.
Workaround:
Software should not execute a floating point instruction directly after a MOV SS or POP
SS instruction.
Status:
For the steppings affected, see the
BD35.
Core C6 May Clear Previously Logged TLB Errors
Problem:
Following an exit from core C6, previously logged TLB (Translation Lookaside Buffer)
errors in IA32_MCi_STATUS may be cleared.
Implication:
Due to this erratum, TLB errors logged in the associated machine check bank prior to
core C6 entry may be cleared. Provided machine check exceptions are enabled, the
machine check exception handler can log any uncorrectable TLB errors prior to core C6
entry. The TLB marks all detected errors as uncorrectable.
