Functional Architecture
Intel® Server Boards SE7320SP2 and SE7525GP2
Revision
4.0
18
3.3.1
Memory Controller Hub (MCH)
The MCH integrates four functions into a single 1077-ball FC-BGA package:
Front side bus
Memory controller
PCI Express* controller
Hub link interface
3.3.1.1
Front Side Bus (FSB)
The Intel
®
E7525 MCH supports either single- or dual-processor configurations using Intel
®
Xeon
®
processors designed for the 800-MHz system bus. The MCH supports a base system
bus frequency of 200 MHz. The address and request interface is double pumped to 400 MHz
while the 64-bit data interface (+ parity) is quad pumped to 800 MHz. This provides a matched
system bus address and data bandwidths of 6.4 GB/s.
3.3.1.2
MCH Memory Sub-System Overview
The Intel
®
E7525 MCH provides an integrated memory controller for direct connection to two
channels of registered DDR266, DDR333 or DDR2-400 memory (stacked or unstacked). Peak
theoretical memory data bandwidth using DDR266 technology is 4.26 GB/s and 5.33 GB/s for
DDR333 technology. For DDR2-400 technology, this increases to 6.4 GB/s.
When both DDR channels are populated and operating, they function in lock-step mode. For the
Intel E7525 MCH, the maximum supported memory size at DDR266, DDR333 or DDR2-400 is
12 GB. On the Server Board SE7525GP2, the maximum supported memory size at DDR266 or
DDR333 is 8 GB. DDR2-400 memory is not supported on this server board.
There are several RASUM (reliability, availability, serviceability, usability, and manageability)
features built into the Intel E7525 MCH memory interface:
DIMM sparing allows for one DIMM per channel to be held in reserve and brought on-
line if another DIMM in the channel becomes defective.
Hardware periodic memory scrubbing, including demand scrub support.
Retry on uncorrectable memory errors.
x4 SDDC (Single Device Data Correction) for memory error detection and correction of
any number of bit failures in a single x4 memory device.
Summary of Contents for SE7320SP2 - 800MHZ Ecc Ddr Xeon
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