Intel Pentium III Processor/840, Manual, Page: 28 / 151

3-4 Intel
®
Pentium
®
III Processor/840 Development Kit Manual
Theory of Operation
3.3.3.1 Memory Controller Hub (MCH)
The Memory Controller Hub (MCH) differentiates the Intel 840 chipset from other Intel 800 series
chipsets. The MCH provides graphics support for AGP 1X/2X/4X, dual RDRAM memory
channels, and multiple PCI segments for high performance I/O.
MCH features:
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544-pin micro Ball Grid Array (micro-BGA) package
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Supports 32- or 36-bit host bus addressing
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8-deep in-order-queue
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ECC protection on PSB data signals
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Parity protection on address and response signals
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Dual Direct RDRAM channels in lock step
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AGP 2.0 graphics port capable of 1X/2X/4X transfers
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266-Mbyte/s AHA_A interface to ICH
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533-Mbyte/s AHA_B interface between MCH and P64H
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ACPI 1.0 and APM 1.2 compliant
3.3.3.2 I/O Controller Hub (ICH)
The I/O Controller Hub (ICH) utilizes Intel Accelerated Hub Architecture to make a direct
connection to the MCH. The ICH supports 32-bit PCI, IDE controllers and dual USB ports. The
ICH is a highly integrated multifunctional I/O Controller Hub that provides the interface to the PCI
Bus and integrates many of the functions needed in today’s applied computing platforms. The ICH
communicates with the host controller over a dedicated hub interface. There are two versions of the
ICH (82801AA: ICH and 82801AB: ICH0). This provides added flexibility in designing cost-
effective system solutions. These devices are pin-compatible and are in 241-pin packages. This
evaluation kit implements the 82801AA version of the ICH.
ICH features:
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241-pin BGA package
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IDE Accelerator supports four independent IDE devices
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Dual channel Fast IDE interface, supports mode 4 and Ultra DMA drives; also supports DMA
bus mastering drives and ATAPI CD-ROMs.
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Dual Universal Serial Bus channels
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5 V PCI interface, Rev 2.2 compliant
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Supports up to six PCI masters
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LPC Bus Support
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Integrated system power management supporting APM 1.2 and ACPI 1.0
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Integrated Real Time Clock
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CMOS battery-backed RAM, 128 bytes
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Nine Dedicated GPIO bits, 20 Multiplexed GPIO bits