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PD672X/30/32/33 — ZV Port
Implementation

Application Note

May 2001

As of May 2001, this document replaces the Basis Communications Corp. document AN-PD10.

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Summary of Contents for PD672X

Page 1: ...PD672X 30 32 33 ZV Port Implementation Application Note May 2001 As of May 2001 this document replaces the Basis Communications Corp document AN PD10...

Page 2: ...y time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have n...

Page 3: ...ntation for Audio DAC 10 7 0 ZV Port Implementation for Socket A and B 11 8 0 Layout Guidelines 15 Figures 1 Typical ZV Port Implementation 7 2 Dedicated Socket Approach to ZV Port Implementation 9 3...

Page 4: ...4 Application Note PD672X 30 32 33 ZV Port Implementation...

Page 5: ...ely compatible with the standards of PCMCIA Personal Card Memory International Association Release 2 0 Standard as well as JEIDA Japan Electronic Industry Development Association Version 4 1 Standard...

Page 6: ...ta on the same signals Video signals from the PC Card are routed to the ZV Port capable video controller audio signals from the PC Card are routed to the ZV Port compliant audio DAC in the host system...

Page 7: ...iance with the ZV Port standard By disabling or powering down the ZV Port this connection between the GD7XXX and the PC Card bus does not interfere with the normal non multimedia PC Card bus operation...

Page 8: ...is implies that the user inserts the multimedia PC Card into either slot and the system is able to recognize and respond to this event appropriately To allow the multimedia PC Card to be inserted into...

Page 9: ...ler used a buffer may be required between the PC Card bus and the audio controller The designer must ensure that while in R2 PC Card mode non ZV operation the traffic over the bus does not cause the a...

Page 10: ...roller when the socket is not configured in ZV Port mode is shown in Figure 3 This illustrates how to control the buffer enable if the GD7XXX is used then one of the GPO pins can control the buffer en...

Page 11: ...in ZV Port Mode PD6722S ocket A PD6722S ocket B Comments 8 A10 I HREF O 21 85 Horizontal sync to ZV Port 10 A11 I VSYNC O 25 89 Vertical sync to ZV Port 11 A9 I Y0 O 28 91 Video data to ZV Port 12 A8...

Page 12: ...TA O 59 122 Audio PCM Data signal Table 2 PC Card ZV Port and PD6729 Pin Assignment Sheet 1 of 2 PC Card Pin Number PC Card Pin I O in PC Card Mode ZV Port Pin Name I O in ZV Port Mode PD6729S ocket A...

Page 13: ...heet 1 of 2 PC Card Pin No PC Card Pin I O in PC Card Mode ZV Port Pin Name I O in ZV Port Mode PD6730 or PD6832 Socket A PD6730 or PD6832 Socket B Comments 8 A10 I HREF O 73 149 Horizontal sync to ZV...

Page 14: ...UV0 O 92 168 Video data to ZV Port 53 A22 I UV1 O 94 170 Video data to ZV Port 54 A23 I UV3 O 96 172 Video data to ZV Port 55 A24 I UV5 O 99 174 Video data to ZV Port 56 A25 I UV7 O 102 176 Video data...

Page 15: ...Vias have already been included in this recommended stub length Maximum total capacitive loading for each Card bus signal 22 pF Maximum input capacitance of each host controller pin 10 pF Maximum inpu...

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