Intel PCH-LP, Programming Manual

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Descriptor Overview
Erase Opcode (EO) and Block/Sector Erase Size (BSES) should be set based on
the flash part and the firmware on the platform. For Intel
®
ME enabled platforms this
should be 4 KB.
Write Status Required (WSR) or Write Enable on Write Status (WEWS) should
be set on flash devices that require an opcode to enable a write to the status register.
Intel
®
ME Firmware will write a 00h to status register to unlock the flash part for every
erase/write operation. If this bit is set on a flash part that has non-volatile bits in the
status register then it may lead to pre-mature wear out of the flash.
• Set the WSRbit to 1b and WEWS to 0b if the Enable Write Status Register opcode
(50h) is needed to unlock the status register. Opcodes sequence sent to SPI flash
will bit 50h 01h 00h.
• Set the WSR bit to 1b AND WEWS bit to 1b if write enable (06h) will unlock the
status register. Opcodes sequence sent to SPI flash will bit 06h 01h 00h.
• Set the WSR bit to 0b AND WEWS bit to 0b or 1b, if write enable (06h) will unlock
the status register. Opcodes sequence sent to SPI flash will bit 06h
• WSR or WEWS should be not be set on devices that use non volatile
memory for their status register. Setting this bit will cause operations to be
ignored, which
may cause undesired operation. Ask target flash vendor if this is the
case for the target flash. See
356H
6.1 Unlocking SPI Flash Device Protection for
Broadwell PCH-LP Platform and
358H
6.2 Locking SPI Flash via Status Register for more
information.
Erase Opcode (EO) and Block/Sector Erase Size (BES) should be set based on the
flash part and the firmware on the platform.
Write Granularity (WG) bit should be set based on the capabilities of the flash
device. If the flash part is capable of writing 1 to 64 bytes (or more) with the 02h
command you can set this bit 0 or 1. Setting this bit high will result in faster write
performance. If flash part only supports single byte write only, then set this bit to 0.
Bit ranges 31:16 and 7:5 are reserved and should set to all zeros.
4.4.3 Intel
®
ME VSCC Table Settings for Broadwell PCH-LP
Family Systems
To understand general guidelines for BIOS VSCC settings on different SPI flash devices,
please refer to VSCCommn.bin Content application note (VSCCommn_bin
Content.pdf under Flash Image Tool directory).
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