Intel PCH-LP, Programming Manual

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Descriptor Overview
4.1.3.3 FLREG2—Flash Region 2 (Intel® ME) Register
(Flash Descriptor Records)
Memory Address: FRBA + 008h Size: 32 bits
4.1.3.4 FLREG3—Flash Region 3 (GbE) Register
(Flash Descriptor Records)
Memory Address: FRBA + 00Ch Size: 32 bits
4.1.3.5 FLREG4—Flash Region 4 (Platform Data) Register
(Flash Descriptor Records)
Memory Address: FRBA + 010h Size: 32 bits
Note: Flash Region 5 (FRBA + 014h) and Region 6 (FRBA + 018h) is reserved in client
platform and should set to 7FFFh.
Bits Description
31
Reserved
30:16
Region Limit. This specifies bits 26:12 of the ending address for this Region.
Notes:
1.Ensure size is a correct reflection of actual Intel
®
ME firmware size that will be used in the
platform
2.Region limit address Bits[11:0] are assumed to be FFFh
15 Reserved
14:0 Region Base. This specifies address bits 26:12 for the Region Base.
Bits Description
31 Reserved
30:16
Region Limit. This specifies bits 26:12 of the ending address for this Region.
Notes:
1.The maximum Region Limit is 128KB above the region base.
2.If the GbE region is not used, the Region Limit must be programmed to 0000h
3.Region limit address Bits[11:0] are assumed to be FFFh
15
Reserved
14:0
Region Base. This specifies address bits 26:12 for the Region Base.
Note: If the GbE region is not used, the Region Base must be programmed to 7FFFh
Bits Description
31
Reserved
30:16
Region Limit. This specifies bits 26:12 of the ending address for this Region.
Notes:
1.If PDR Region is not used, the Region Limit must be programmed to 0000h
2.Ensure BIOS region size is a correct reflection of actual BIOS image that will be used in the
platform
3.Region limit address Bits[11:0] are assumed to be FFFh
15 Reserved
14:0
Region Base. This specifies address bits 26:12 for the Region Base.
Note: If the Platform Data region is not used, the Region Base must be programmed to 7FFFh