Intel PCH-LP, Programming Manual

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Descriptor Overview
4.1.1.2 FLMAP0 - Flash Map 0 Register
(Flash Descriptor Records)
Memory Address: FDBAR + 014h Size: 32 bits
4.1.1.3 FLMAP1—Flash Map 1 Register
(Flash Descriptor Records)
Memory Address: FDBAR + 018h Size: 32 bits
Recommended Value:15100206h
Bits Description
31:27 Reserved
26:24
Number Of Regions (NR). This field identifies the total number of Flash Regions. This number is
0's based, so a setting of all 0's indicates that the only Flash region is region 0, the Flash Descriptor
region.
23:16
Flash Region Base Address (FRBA). This identifies address bits [11:4] for the Region portion of
the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
Set this value to 04h. This will define FRBA as 40h.
15:10 Reserved
9:8
Number Of Components (NC). This field identifies the total number of Flash Components. Each
supported Flash Component requires a separate chip select.
00 = 1 Component
01 = 2 Components
All other settings = Reserved
7:0
Flash Component Base Address (FCBA). This identifies address bits [11:4] for the Component
portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
set this field to 03h. This will define FCBA as 30h
Bits Description
31:24
PCH Strap Length (PSL). Identifies the 1s based number of Dwords of PCH Straps to be read, up
to 255 DWs (1KB) max. A setting of all 0's indicates there are no PCH DW straps.
This field MUST be set to 15h
23:16
Flash PCH Strap Base Address (FPSBA). This identifies address bits [11:4] for the PCH Strap
portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
Set this field to 10h. This will define FPSBA to 100h
15:10 Reserved
9:8
Number Of Masters (NM). This field identifies the total number of Flash Masters.
Set this field to 10b
7:0
Flash Master Base Address (FMBA). This identifies address bits [11:4] for the Master portion of
the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
Set this field to 06h. This will define FMBA as 60h