Intel MultiProcessor Specification Download Page 1

Page: 1 / 97

MultiProcessor

Specification

Version 1.

May

1997

Summary of Contents for MultiProcessor

Page 1: ...MultiProcessor Specification Version 1 4 May 1997...

Page 2: ...liability for infringement of any proprietary rights relating to implementation of information in this specification Intel does not warrant or represent that such implementation s will not infringe su...

Page 3: ...this specification Previously this was indicated by bit 0 of MP Feature Information Byte 1 3 One more hardware default system configuration was added for MCA PCI with the integrated APIC 4 11 94 002 M...

Page 4: ......

Page 5: ...1 4 I O Expansion Bus 2 4 2 2 BIOS Overview 2 5 2 3 Operating System Overview 2 5 Chapter 3 Hardware Specification 3 1 System Memory Configuration 3 1 3 2 System Memory Cacheability and Shareability 3...

Page 6: ...1 Processor Entries 4 7 4 3 2 Bus Entries 4 10 4 3 3 I O APIC Entries 4 12 4 3 4 I O Interrupt Assignment Entries 4 12 4 3 5 Local Interrupt Assignment Entries 4 15 4 4 Extended MP Configuration Tabl...

Page 7: ...r Startup B 3 B 4 1 USING INIT IPI B 4 B 4 2 USING STARTUP IPI B 5 B 5 AP Shutdown Handling B 5 B 6 Other IPI Applications B 6 B 6 1 Handling Cache Flush B 6 B 6 2 Handling TLB Invalidation B 6 B 6 3...

Page 8: ...Entry 4 10 4 6 I O APIC Entry 4 12 4 7 I O Interrupt Entry 4 13 4 8 Local Interrupt Entry 4 15 4 9 System Address Space Entry 4 18 4 10 Example System with Multiple Bus Types and Bridge Types 4 19 4...

Page 9: ...17 4 14 System Address Space Mapping Entry Fields 4 19 4 15 Bus Hierarchy Descriptor Entry Fields 4 22 4 16 Compatibility Bus Address Space Modifier Entry Fields 4 24 4 17 Predefined Range Lists 4 24...

Page 10: ......

Page 11: ...specific buses 1 1 Goals The intent of this specification is to establish an MP Platform interface standard that extends the performance of the existing PC AT platform beyond the traditional single p...

Page 12: ...that multiprocessor systems can be implemented Vendors may for example create noncompliant high performance scalable multiprocessor systems that do not have the PC AT compatibility required by this sp...

Page 13: ...ither those who create general purpose BIOS products or those who modify these products to suit specific MP hardware Operating system developers who will be adapting MP operating systems to run on the...

Page 14: ...at the bottom and the highest addresses at the top of the illustration as shown in Figure 1 2 Bit positions are numbered from right to left RESERVED RESERVED THREE BYTE FIELD RESERVED 00H 04H 08H 0CH...

Page 15: ...d access that space by the same addresses Memory symmetry offers a very important feature the ability for all processors to execute a single copy of the operating system Any existing system and applic...

Page 16: ...ntium 735 90 and 815 100 processors Software transparent cache and shared memory subsystem Software visible components of the PC AT platform 2 1 1 System Processors To maintain compatibility with exis...

Page 17: ...nterrupt control functions are distributed between two basic functional units the local unit and the I O unit The local and I O units communicate through a bus called the Interrupt Controller Communic...

Page 18: ...the exception of addresses 0A_0000h through 0F_FFFFh and 0FFFE_0000h through 0FFFF_FFFFh which are reserved for I O devices and the BIOS Compared to a uniprocessor system a symmetric multiprocessor sy...

Page 19: ...insert an MP floating pointer structure in the standard BIOS The cost of this level of simplicity in the BIOS however is that the system developer has less flexibility in the design of the hardware A...

Page 20: ......

Page 21: ...osted memory writes Multiprocessor interrupt control Reset support Interval timer usage Support for fault resilient booting While the bulk of the MP hardware specification pertains to multiprocessor i...

Page 22: ...PED I O SPACE PART OF THIS SPECIFICATION UNSHADED ADDRESS REGIONS ARE FOR REFERENCE ONLY AND SHOULD NOT BE CONSTRUED AS THE SOLE DEFINITION OF A PC AT COMPATIBLE ADDRESS SPACE Figure 3 1 System Memory...

Page 23: ...0FECF_FFFFh 1 APIC I O unit Yes No Refer to the register description in the APIC data book 0FED0_0000h 0FEDF_FFFFh Reserved for memory mapped I O devices Yes 2 Not specified 0FEE0_0000h 0FEEF_FFFFh 1...

Page 24: ...che flush instructions under normal circumstances Reliable communication All processors must be able to communicate with each other in a way that eliminates interference when more than one processor a...

Page 25: ...lowing sections describe the APIC architecture and the three interrupt modes allowed in an MP compliant system 3 6 1 APIC Architecture The Intel Advanced Programmable Interrupt Controller APIC is base...

Page 26: ...ns the APIC ID register can be reduced to the least significant 4 bits and the Logical Destination register can be reduced to the most significant 8 bits To ensure software compatibility with all vers...

Page 27: ...a combination of hardware and software The hardware and programming specifications for each of these modes are further defined in the following subsections BIOS programmers should refer to Appendix A...

Page 28: ...ddress and data respectively To access the IMCR write a value of 70h to I O port 22h which selects the IMCR Then write the data to I O port 23h The power on default value is zero which connects the NM...

Page 29: ...PIC is programmed as ExtINT specifying to the APIC that the PIC is to serve as an external interrupt controller Whenever the local APIC finds that a particular interrupt is of type ExtINT it asserts t...

Page 30: ...se the interrupt signal passes through both the I O APIC and the BSP s local APIC LINTIN0 LINTIN1 NMI NMI INTR CPU 1 LINTIN0 LINTIN1 LINTIN0 LINTIN1 NMI INTR CPU 2 NMI INTR CPU 3 REG MARK BSP AP1 AP2...

Page 31: ...TS SHADED AREAS INDICATE UNUSED CIRCUITS DOTTED LINE SHOWS INTERRUPT PATH Figure 3 5 Symmetric I O Mode The APIC I O unit has general purpose interrupt inputs that can be individually programmed to di...

Page 32: ...use interrupt vector 16 to manage floating point exceptions when the system is in symmetric mode It is recommended that hardware platforms be designed to block delivery of floating point exception sig...

Page 33: ...489DX APIC s internal operation 2 The TMBASE pin allows an independent clock signal to be connected to the 82489DX APIC for use by the timer functions The interval timers of the integrated APIC have o...

Page 34: ...l486 processors or the RESET signal of the 82489DX APIC See Section 3 7 1 The term INIT refers to either a system wide soft reset initialization or a processor specific initialization For example the...

Page 35: ...Processor specific INIT A processor specific INIT is one of the basic multiprocessor support functions of a compliant multiprocessor system along with processor startup and shutdown With it the BSP c...

Page 36: ...us The BIOS must disable interrupts to all processors and set the APICs to the system initial state before giving control to the operating system The operating system is responsible for initializing a...

Page 37: ...mon hardware defaults and a maximal method that provides the utmost flexibility in hardware design Figure 4 1 shows the general layout of the MP configuration data structures 00H PHYSICAL ADDRESS POIN...

Page 38: ...em design corresponds to one of the default configurations listed in Chapter 5 Note that these defaults are only for designs that are always equipped with two processors Systems that support a variabl...

Page 39: ...KSUM 08 0CH H 31 0 7 8 15 16 23 24 31 0 7 8 15 16 23 24 PHYSICAL ADDRESS POINTER P 50h _ 5Fh MP FEATURE BYTE 1 MP FEATURE BYTES 2 5 Figure 4 2 MP Floating Pointer Structure Table 4 1 MP Floating Point...

Page 40: ...URE INFORMATION BYTES 3 5 13 24 Reserved for future MP definitions Must be zero The MP feature information byte 1 specifies the MP system default configuration type If nonzero the system configuration...

Page 41: ...ENGTH P 50h P 50h M 4Dh C 43h SIGNATURE 00H 04H CHECKSUM OEM TABLE POINTER OEM TABLE SIZE MEMORY MAPPED ADDRESS OF LOCAL APIC 10H 1CH 20H 24H 08H 31 0 7 8 15 16 23 24 31 0 7 8 15 16 23 24 O E M space...

Page 42: ...t this field is zero ENTRY COUNT 34 16 The number of entries in the variable portion of the base table This field helps the software identify the end of the table when stepping through the entries ADD...

Page 43: ...re reserved 4 3 1 Processor Entries Figure 4 4 shows the format of each processor entry and Table 4 4 defines the fields RESERVED RESERVED 31 0 3 7 4 8 11 12 15 16 19 20 23 24 27 28 CPU SIGNATURE LOCA...

Page 44: ...n flags for the processor as returned by the CPUID instruction Refer to Table 4 6 for values If the processor does not have a CPUID instruction the BIOS must assign values to FEATURE FLAGS according t...

Page 45: ...releases information about stepping numbers as needed Table 4 6 Feature Flags from CPUID Instruction Bit Name Description Comments 0 FPU On chip Floating Point Unit The processor contains an FPU that...

Page 46: ...y and Table 4 7 explains the fields of each entry 00H 04H 31 0 7 8 15 16 23 24 31 0 7 8 15 16 23 24 ENTRY TYPE 1 BUS ID BUS TYPE STRING Figure 4 5 Bus Entry Table 4 7 Bus Entry Fields Field Offset in...

Page 47: ...US ID if any one of the following criteria are true 1 The bus does not share its memory address space with another bus 2 The bus does not share its I O address space with another bus 3 The bus does no...

Page 48: ...ies indicate which interrupt source is connected to each I O APIC interrupt input There is one entry for each I O APIC interrupt input that is connected Figure 4 7 shows the format of each entry and T...

Page 49: ...c knowledge of bus interrupt schemes in order to support the bus This operating system bus specific knowledge is beyond the scope of this specification 00H 04H 31 0 7 8 15 16 23 24 ENTRY TYPE 3 INTERR...

Page 50: ...of APIC I O input signals 00 Conforms to specifications of bus for example ISA is edge triggered 01 Edge triggered 10 Reserved 11 Level triggered SOURCE BUS ID 4 8 Identifies the bus from which the i...

Page 51: ...ernal PIC the source is the 8259 INTR output line and the vector is supplied by the 8259 All other values are reserved 4 3 5 Local Interrupt Assignment Entries These configuration table entries tell w...

Page 52: ...cal input signals 00 Conforms to specifications of bus for example ISA is edge triggered 01 Edge triggered 10 Reserved 11 Level triggered SOURCE BUS ID 4 8 Identifies the bus from which the interrupt...

Page 53: ...pe when parsing this section of the table should ignore the content and move on to the next entry until the offset from the end of the base table reaches the length that is specified in the EXTENDED T...

Page 54: ...es thereby decreasing the amount of bus traffic on a given bus and increasing the overall system performance Each consecutive address range that is usable by the operating system to access devices on...

Page 55: ...are reserved ADDRESS BASE 4 64 Starting address LENGTH 12 64 Number of addresses which are visible to the bus If any main memory address is mapped to a software visible bus such as PCI it must be expl...

Page 56: ...discover the address space mapping by querying the PCI to PCI bridge specification compliant bridge directly 2 For buses that are connected via a parent I O bus and for which the subtractive decode b...

Page 57: ...e system hierarchically below another I O bus For example given the system described in Figure 4 10 bus hierarchy entries are required for the EISA bus and the PCI BUS 2 since both have parent buses t...

Page 58: ...NT BUS 4 8 Parent Bus This number corresponds to the BUS ID as defined in the base table bus entry for the parent bus of this bus For buses where the BUS INFORMATION SD bit is set System Address Mappi...

Page 59: ...pport ISA devices to avoid any potential conflict The same effect can be achieved by using System Address Space Mapping entries to completely describe the address ranges supported on a bus including t...

Page 60: ...to zero the specified address ranges are to be added to the address space associated with the bus PREDEFINED RANGE LIST 4 32 A number that indicates the list of predefined address space ranges that t...

Page 61: ...d description of the MP floating pointer structure To use a default configuration a system must meet the following basic criteria 1 The system supports two processors 2 Both processors must execute th...

Page 62: ...ut without EISA bus logic with inverters before I O APIC inputs 1 15 8 255 Reserved for MP future use The default system configurations are designed to support dual processor systems with fixed config...

Page 63: ...I RESET INTR LOCAL 82489DX APIC CPU 1 NMI INTR PRST PNMI PINT LINTIN0 LINTIN1 LOCAL 82489DX APIC NMI INTR CPU 3 IMCR I O BUS ExtINTA INTA TRAP ExtINTA INTA TRAP INTEL486 RESET GLUE INTEL486 E0 REG MAR...

Page 64: ...nal to a signal that is acceptable to edge triggered input pins such as INTIN0 or LINTIN0 If the AP used in these configurations does not automatically HALT after RESET or INIT the AP must be prevente...

Page 65: ...12 14 15 IRQ13 EISA DMA CHAINING FERR IGNNE FERR SAMPLING FROM BSP EDGE LEVEL TRIGGER POLARITY CONTROL 12 ABFULL PS 2 MOUSE LITM3 7 9 12 14 15 LITMx IRQx ABFULL SAMPLING 12 13 PIRQ MAPPING PIRQ0 3 3...

Page 66: ...pt request line IRQ assignments are connected to the I O APIC in each of the default configurations Table 5 2 Default Configuration Interrupt Assignments First I O APIC INTINx Config 1 Config 2 Config...

Page 67: ...patible buses such as EISA and MCA support active low level triggered interrupts If these types of buses are to be incorporated in a compliant system external inverters must be implemented to ensure t...

Page 68: ...rating system must leave the LINTIN1 of all local APICs disabled to ensure that the BSP is the only processor that receives the NMI In PIC Mode configurations the 8259 INTR signal also follows the sam...

Page 69: ...lains this in more detail A 1 BIOS Post Initialization Once system power is applied or the reset button is pressed if the system is so equipped a hardware circuit generates a system RESET sequence to...

Page 70: ...sting uniprocessor software the system BIOS must initialize and enable the BSP s APIC first The local unit must be programmed to function as a virtual wire which delivers the CPU interrupt from the 82...

Page 71: ...on switch into real big mode The APIC spurious interrupt must point to a vector whose lower nibble is 0F that is 0xF where x is 0 F Here we use Int 00FH which handles spurious interrupts and supplies...

Page 72: ...he MP configuration table Because the MP configuration table is optional the BIOS must set the MP feature information bytes in the MP floating pointer structure to indicate whether an MP configuration...

Page 73: ...al APIC ID from the Local Unit ID Register and uses this information to complete its entry in the MP configuration table 2 Just prior to exiting the BIOS the AP clears its status flag to signal the BS...

Page 74: ......

Page 75: ...with the BIOS The rest of the processors are designated as the application processors APs The BSP is responsible for booting the operating system Once the MP operating system is up and running the BS...

Page 76: ...if they occur If the MP configuration table does not exist the BSP configures the operating system for the default system configuration indicated by the default configuration bits of the MP feature in...

Page 77: ...s AP a STARTUP IPI BSP DELAYs 200 SEC BSP sends AP a STARTUP IPI BSP DELAYs 200 SEC BSP verifies synchronization with executing AP Example B 1 Universal Start up Algorithm If the MP configuration tabl...

Page 78: ...functional The following two sections describe specifics relating to the use of INIT and STARTUP IPIs that can be used to guide the implementation of the universal algorithm presented here B 4 1 USING...

Page 79: ...ect is to set CS IP to VV00 0000h For an operating system to use a STARTUP IPI to wake up an AP the address of the AP initialization routine or of a branch to that routine must be in the form of 000VV...

Page 80: ...to powering down a processor Should a system wide cache flush be necessary the operating system should use the broadcast IPI mechanism to request that each of the processors write back and invalidate...

Page 81: ...upt generated by the Local APIC Error Register 0xFEE00370 B 8 Supporting Unequal Processors Some MP operating systems that exist today do not support processors of different types speeds or capabiliti...

Page 82: ......

Page 83: ...m support either PIC Mode or Virtual Wire Mode at power on Is Symmetric I O Mode implemented Are all APIC IDs unique Are all local APIC IDs assigned by hardware or BIOS Do local APIC IDs begin with ze...

Page 84: ......

Page 85: ...oot from a disk connected to a PCI controller on a second PCI bus for example To prevent double delivery of this PCI interrupt once the system switches to symmetric I O mode for an MP operating system...

Page 86: ...tings cannot be disabled or altered This situation implies two restrictions that must be placed on the way PCI interrupts are routed to EISA ISA IRQs and on that way the MP configuration table is buil...

Page 87: ...appear in ascending order by bus ID number This specific interpretation of the information presented in Table 4 7 ensures consistency between the information in the MP configuration table and the mode...

Page 88: ......

Page 89: ...data structure in multiples of 16 bytes Currently only one 16 byte data structure is defined It must span a minimum of 16 contiguous bytes beginning on a 16 byte boundary and it must be located within...

Page 90: ...tion as defined in Chapter 5 is implemented by the system MP FEATURE INFORMATION BYTE 2 12 0 12 6 12 7 6 1 1 Bits 0 5 Reserved for future MP definitions Bit 6 Multiple Clock Sources When set this bit...

Page 91: ...ses that are visible on a particular bus Each bus defined in the Base Table can have any number of System Address Space Mapping entries included in the Extended Table Thus individual buses can be conf...

Page 92: ...tarting address LENGTH 12 64 Number of addresses which are visible to the bus If any main memory address is mapped to a software visible bus such as PCI it must be explicitly declared using a System A...

Page 93: ...oller For buses with fewer than 32 bit address lines all real memory at addresses that the bus can generate must be accessible for DMA 4 4 2 Bus Hierarchy Descriptor Entry If present Bus Hierarchy Des...

Page 94: ...The BUS ID identity of this bus This number corresponds to the BUS ID as defined in the base table bus entry for this bus BUS INFORMATION SD 3 0 1 Subtractive Decode Bus If set all addresses visible...

Page 95: ...lly connected 8259A equivalent PIC The ExtINTA output signal is also asserted The INTA cycle that corresponds to the ExtINT delivery should be routed to the external PIC that is expected to supply the...

Page 96: ...In this mode the APICs are fully functional and interrupts are generated and delivered to the processors by the APICs Any interrupt can be delivered to any processor This is the only multiprocessor in...

Page 97: ...Order Number 242016 006 Printed in U S A...

Search results

Summary of Contents for MultiProcessor

Reviews:

Related manuals for MultiProcessor

Brands by name

Popular brands

Intel MultiProcessor, Specification

Search results

Summary of Contents for MultiProcessor

Reviews:

Related manuals for MultiProcessor

Brands by name

Popular brands