Intel M50CYP2UR Series, System Integration And Service Manual

Page: 132 / 162

Intel® Server System M50CYP2UR Family System Integration and Service Guide
132
Table 8. POST Progress Code LED Example
LEDs
Upper Nibble AMBER LEDs Lower Nibble GREEN LEDs
MSB LSB
LED #7 LED #6 LED #5 LED #4 LED #3 LED #2 LED #1 LED #0
8h 4h 2h 1h 8h 4h 2h 1h
Status ON OFF ON OFF ON ON OFF OFF
Read
Value
Binary 1 0 1 0 1 1 0 0
Hexadecimal A h C h
Result AC h
Upper nibble bits = 1010b = A h; Lower nibble bits = 1100b = C h; the two Hex Nibble values are combined to
create a single AC h POST Progress Code.
E.1 Early POST Memory Initialization MRC Diagnostic Codes
Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Table 9. MRC Progress Codes
Post Code
(Hex)
Upper Nibble Lower Nibble
Description
8h 4h 2h 1h 8h 4h 2h 1h
B0 1 0 1 1 0 0 0 0
Detect DIMM population
B1 1 0 1 1 0 0 0 1
Set DDR4 frequency
B2 1 0 1 1 0 0 1 0
Gather remaining SPD data
B3 1 0 1 1 0 0 1 1
Program registers on the memory controller level
B4 1 0 1 1 0 1 0 0
Evaluate RAS modes and save rank information
B5 1 0 1 1 0 1 0 1
Program registers on the channel level
B6 1 0 1 1 0 1 1 0
Perform the JEDEC defined initialization sequence
B7 1 0 1 1 0 1 1 1
Train DDR4 ranks
1 0 0 0 0 0 0 0 1
Train DDR4 ranks
2 0 0 0 0 0 0 1 0
Train DDR4 ranks – Read DQ/DQS training
3 0 0 0 0 0 0 1 1
Train DDR4 ranks – Receive enable training
4 0 0 0 0 0 1 0 0
Train DDR4 ranks – Write DQ/DQS training
5 0 0 0 0 0 1 0 1
Train DDR4 ranks – DDR channel training done
B8 1 0 1 1 1 0 0 0
Initialize CLTT/OLTT
B9 1 0 1 1 1 0 0 1
Hardware memory test and init
BA 1 0 1 1 1 0 1 0
Execute software memory init