Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
857
Synchronous Serial Port—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
20.0
Synchronous Serial Port
The Synchronous Serial Port (SSP) is a full-duplex synchronous serial interface. It can
connect to a variety of external analog-to-digital (A/D) converters, audio and telecom
codecs, and many other devices that use serial protocols for transferring data. It
supports National Microwire*, Texas Instruments* synchronous serial protocol (SSP),
and Motorola* serial peripheral interface (SPI) protocol.
The SSP operates in master mode (the attached peripheral functions as a slave), and
supports serial bit rates from 7.2 KHz to 1.84 MHz. Serial data formats may range from
4 to 16 bits in length. Two on-chip register blocks function as independent FIFOs for
data, one for each direction. The buffers are 16 entries deep x 16 bits wide.
Buffers may be loaded or emptied by the system processor using SRAM-like transfers.
The transfers are always one word per transfer. Each 32-bit word from the system fills
one entry in a FIFO using the lower half 16-bits of a 32-bit word.
20.1
SSP Operation
Serial data is transferred between the system and an external peripheral through FIFO
buffers in the SSP Port. Transfers are initiated by the host processor to/from system
memory. Operation is full duplex — separate buffers and serial data paths permit
simultaneous transfers in both directions.
20.1.1
Processor-Initiated Data Transfer
Transmit data (system to peripheral) is written by host processor to SSP Port
“Transmit” buffer. The buffer works as a FIFO, and is seen as one 32-bit location by the
processor. The SSP Port then takes the data from the buffer, serializes it, and sends it
over the serial wire (SSP_TXD) to the peripheral.
Received data from peripheral (on SSP_RXD) converted to parallel words and stored in
“Receive” FIFO buffer. A programmable “fullness” threshold, when passed, triggers an
interrupt to the interrupt controller (hence, if enabled, to an interrupt input to the
CPU). Interrupt service routine responds by identifying source of interrupt and then
doing an SRAM-like read from inbound FIFO buffer. All buffer reads and writes use SPB
to transfer data between internal CPU system bus and the buffer.
The host processor differentiates between the two FIFOs by whether it does a READ or
a WRITE transfer. Reads automatically target the Receive FIFO, while writes will write
data to the Transmit FIFO. From a memory map point of view, they are at the same
address.
FIFO buffers are 16 words deep x 16 bits wide. This stores up to 16 samples per buffer.
