Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Expansion Bus
Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
688
Order Number: 306262-004US
12.4.3.2
External Arbiter
If the external arbiter is enabled, the Expansion bus controller request line is called
EX_GNT_REQ_N and its grant signal is called EX_REQ_GNT_N. EX_REQ_N is ignored
and pull-ups in the PAD I/O block are enabled to avoid a floating input. When the
Expansion bus controller needs access to the Expansion bus, the Expansion bus
controller will assert request. As soon as the Expansion bus controller is granted the
bus, the Expansion bus controller may start a data transfer. The Expansion bus
controller will keep the request line asserted until all phases (T1,T2,T3,T3,T5) of the
data transfer are complete. If there is not another data transfer to be performed, the
Expansion bus controller will deassert request. After the Expansion bus controller
deasserts request, the external arbiter can deassert grant. The external arbiter must
not deassert grant until request is deasserted.
If the external arbiter parks grant on the Expansion bus controller, the Expansion bus
controller will not start a data transfer until two cycles after it has asserted request
assuming it still is granted the bus. The Expansion bus controller must wait 2 cycles
with request asserted to ensure the external arbiter does not remove the grant the
same cycle as request is asserted. Refer to
“External Expansion Bus Timing Diagram”
for more details.
12.4.4
Multiple Processors Connected by the Expansion Bus
When connecting multiple IXP45X/IXP46X network processors together via the
Expansion bus, a special reset sequence is required to ensure that each of the IXP45X/
IXP46X network processors has independent configuration values as defined in
“Configuration Register 0” on page 706
In order to boot multiple IXP45X/IXP46X network processors, the system must assert
the RESET_IN_N pin to processors #0 and #1 upon power up. The Expansion bus
controller has weak pull-ups on all shared Expansion bus signals to prevent floating
during reset. After the board configures the appropriate EX_ADDR configuration straps,
RESET_IN_N can be deasserted on processor #0. Processor #0 will began to boot,
however processor #1 will remain in reset. Typically processor #0 will be the Expansion
bus arbiter and processor #1 will use processor #0 as the arbiter.
After the boot sequence is complete for processor #0, an outbound read or write needs
to be issued to the Expansion bus to force EX_ADDR to the appropriate configuration
values for processor #1. Once EX_ADDR is stable, RESET_IN_N can be deasserted for
processor #1. The system designer can use a GPIO pin on processor #0 to signal that
EX_ADDR is stable.
When programming the EXP_TIMING_CS register to access other IXP45X/IXP46X
network processors, T3 must be programmed with a minimum of 3 clocks, T5 must be
programmed to either 0, 1, or 2 clocks, WORD_EN must be set to 32-bit bus, MUX_EN
must be 0, CYC_TYP must be programmed to Intel Cycles, and EXP_CHIP must be set
to 1. T1,T2, and T4 can be programmed to any value, but typically they are left at 0
clocks.
When connecting multiple IXP45X/IXP46X network processors together via the
Expansion bus, the GrantRemove bit must be clear. This requirement is necessary to
guarantee that the Expansion master will never lose grant during the T1-address timing
shows the connection of multiple IXP45X/IXP46X
network processors.
