Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
663
Expansion Bus Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors
12.4.1.6
Parity
The Expansion bus controller generates even or odd parity for each byte written to
EX_DATA and compares parity for each byte read on EX_DATA, if PAR_EN is set in each
EXP_TIMING_CS register. EX_PARITY is transferred in the same clock cycle in which
EX_DATA is transferred. If a read transfer results in a parity mismatch on EX_PARITY,
the AHB address is logged in the EXP_PARITY_STATUS and OutErrorSts is set. The
Expansion bus controller will then respond with an AHB error response on the first data
cycle, even if the parity error does not occur on the first data cycle on the Expansion
bus. Exp_parity_error will be asserted by the Expansion bus controller during a parity
error and an interrupt will be generated if enabled in the interrupt controller.
Exp_parity_error will remain asserted until software clears EXP_PARITY_STATUS
register.
Even parity is defined as the number of 1’s on EX_DATA[7:0] and EX_PARITY[0] must
be an even number. For example, if EX_DATA[7:0] = 0x25, EX_PARITY[0] must be 1,
since there are 3 bits set on 0x25 and there needs to be an even number of 1s. Parity
for the second byte of EX_DATA is generated on EX_PARITY[1]; the third byte of
EX_DATA is generated on EX_PARITY[2], and the 4th byte of EX_DATA is generated on
EX_PARITY[3]. For 16-bit devices, EX_DATA[31:16] is not used and EX_PARITY[3:2]
should not toggle and is ignored for reads. For 8-bit devices, EX_DATA[31:8] is not
used and EX_PARITY[3:1] should not toggle and is ignored for reads. For 32-bit
devices, byte and halfword writes should not toggle EX_PARITY on byte enables that
are not asserted. For 32-bit devices, byte and half-word reads must not compare parity
on bytes that are not read. If PAR_EN is cleared for a particular device, the Expansion
bus controller doesn’t generate or compare parity and EX_PARITY should not toggle to
conserve power. Odd parity can be enabled by setting OddPar in the
EXP_MST_CONTROL register and is equivalent to the inverted value of even parity.
Figure 128. I/O Wait Extended Phase Timing
EX_ CLK
EX_CS_ N[0]
EX_ADDR[23 :0 ]
EX_RD_N
EX_DATA[15:0]
Valid Data
Valid Address
4 Cycles
4 Cycles
16 Cycles
16 Cycles
T1=3 h
T2=3 h
T3=F h
T4=3 h
T5=F h
EX_ IOWAIT_N
B5243- 01
....
4 Cycles
...
.
2 Cycles
