Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
587
Memory Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Note:
If the memory controller is completing transactions from the core processor memory
transaction queue (CMTQ) when the refresh counter expires, the Memory Controller
Arbiter (MARB) will complete the CMTQ tenure based on the
Port Transaction Count Register MPTCR”
, before any refresh cycles are issued. Once
refresh cycles are initiated, all queued refresh transactions are to be completed in a
single tenure.
11.2.1.6
DDRI SDRAM Control Block
The DDRI SDRAM Control Block contains all functionality to process the DDRI SDRAM
data accesses per the transactions issued by the MARB. To process a transaction the
DDRI SDRAM Control Block employs several sub-blocks. The sub-blocks include the
Page Control block, DDRI SDRAM State Machine and Pipeline Queues, and Error
Correction Logic.
11.2.1.6.1
Page Control Block
The Page Control Block records and maintains the open DDRI SDRAM pages. The MCU
can keep a maximum of eight pages open simultaneously (four per bank). This block
keeps track of open pages and determines if the transactions hit an open page. See
Section 11.2.2.6, “Page Hit/Miss Determination”
11.2.1.6.2
DDRI SDRAM State Machine and Pipeline Queues
Since the MCU generates error correction codes based on the data, the MCU is a
pipelined architecture. Pipelining also ensures acceptable AC timings to the memory
interfaces. The DDRI SDRAM state machine pipelines DDRI SDRAM memory operations
for several clocks.
11.2.1.6.3
Error Correction Logic
The Error Correction Logic generates the ECC code for DDRI SDRAM reads and writes.
For reads, this logic compares the ECC codes read with the locally generated ECC code.
If the codes mismatch, then the Error Correction Logic determines the error type. For a
single-bit error, this block determines which bit is in error and corrects the error. For a
single-bit or multi-bit error, the Error Correction Logic logs the error in ELOG0 and
Section 11.2.3, “Error Correction and Detection”
for more details.
11.2.1.7
DDRI SDRAM RCOMP Block
The DDRI RComp circuitry dynamically compensates for variations in operating
conditions due to process, temperature, or voltage. These variations are measured
through a resistive mechanism in a special I/O Pad and evaluated in the associated
compensation circuitry. Adjustments are then made to the drive strength of the buffers
ensuring error free operation over the entire range of operating conditions.
The DDRI RComp circuitry fine-tunes three separate I/O buffer parameters:
• P-Channel drive strength
• N-Channel drive strength
• Buffer slew rate
11.2.2
DDRI SDRAM Memory Support
The memory controller for the IXP45X/IXP46X network processors supports one or two
banks of DDRI SDRAM. DDRI SDRAM allows zero data-to-data wait-state operation.
DDRI SDRAM offers an extremely wide range of configuration options emerging from
the SDRAMs internal interleaving and bursting capabilities.
