Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Develepor’s Manual
Order Number: 306262-004US
577
PCI Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
10.6.2
Error Handling as a PCI Initiator During PCI Direct Access
from the AHB Bus
This section describes error handling procedures when the PCI Initiator Interface
encounters a fatal error condition during a PCI transfer request received from the AHB
Target Interface.
10.6.2.0.1
An AHB Target Read Encountered a Master Abort, Target Abort, PCI_TRDY_N
Timeout, or RETRY Timeout During the PCI Read Operation
Note:
A PCI_TRDY_N timeout occurs if the intended PCI target of the transfer asserts
PCI_DEVSEL_N but fails to assert PCI_TRDY_N or abort the transfer with a Target Abort
within the number of PCI clocks specified in pci_rtotto.TRDYTO. A RETRY Timeout
occurs if the intended target exceeds the number of RETRY responses indicated in
pci_rtotto.RetryTO.
1. If the AHB read operation is not complete, the AHB Target Interface asserts an
ERROR response to terminate the AHB operation. If the AHB read is complete
because the PCI error occurred during a read-ahead transfer, no action is taken. In
either case, the AHB Target Interface blocks any further PCI requests until the error
condition has cleared.
2. The pci_isr.PFE bit is set to indicate a fatal PCI error has occurred.
3. The PCI Configuration Register bits pci_srcr.RMA or pci_srcr.RTA are set if a Master
Abort or Target Abort occurred, respectively.
10.6.2.0.2
An AHB Target Write Encountered a Master Abort, Target Abort, PCI_TRDY_N
Timeout, or RETRY Timeout During the PCI Write Operation
1. The Initiator Request FIFO is flushed and all queued requests are lost. Any data in
the Initiator Transmit FIFO is flushed as well.
2. If the write is still in progress on the AHB bus, an ERROR response is not issued.
The remaining data in the burst is discarded and the AHB transfer completes
normally.
3. The pci_isr.PFE bit is set to indicate a fatal PCI error has occurred.
4. The PCI Configuration Register bits pci_srcr.RMA or pci_srcr.RTA are set if a Master
Abort or Target Abort occurred, respectively.
Caution:
Note that in this error condition, the entire contents of the Initiator Request FIFO is
discarded. Any queued write operations will be lost since they have already been
posted by the AHB Target Interface. A queued read, though flushed from the queue,
will complete since the AHB Master that originated the read must try the transfer again
after getting a RETRY response. After the error condition has cleared, the AHB Target
Interface will request the read again when the master retries the operation.
10.6.2.0.3
The PCI Initiator Interface Detected a Parity Error During a PCI Read
Operation
1. The PCI Initiator Interface ignores the error and continues with the transfer.
2. The pci_isr.PPE bit is set to indicate a PCI parity error has occurred.
3. The PCI Configuration Register bit pci_srcr.DPE is set.
10.6.2.0.4
The Target of a PCI Write Operation Asserted PCI_PERR_N During the
Transfer
1. The PCI Initiator Interface ignores the error and continues with the transfer.
2. The pci_isr.PPE bit is set to indicate a PCI parity error has occurred.
