Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—PCI Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Develepor’s Manual
August 2006
546
Order Number: 306262-004US
There is no byte lane reversal for accesses to PCI Controller CSRs or PCI Configuration
shows the byte lane routing for these types of accesses. A PCI
CSR write with byte enable 2 asserted, for example, will write to bits 23:16 of the
register. An AHB write with Address bits [1:0] = 10b in big-endian mode (pci_csr.ABE =
1) will write bits 15:8 of the register. In little-endian mode (pci_csr.ABE = 0), bits
23:16 will be written.
Figure 99.
Byte Lane Routing During DMA Transfers
B4303-01
31
24
AHB-to-PCI DMA,
DS = 1
AHB Data
3
2
1
0
23
16 15
8
7
0
31
24 23
16 15
8
7
0
31
24
3
2
1
0
23
16 15
8
7
0
31
24 23
16 15
8
7
0
AHB Data
PCI Data
PCI Data
PCI-to-AHB DMA,
DS = 1
31
24
AHB-to-PCI DMA,
DS = 0
AHB Data
3
2
1
0
23
16 15
8
7
0
31
24 23
16 15
8
7
0
31
24
3
2
1
0
23
16 15
8
7
0
31
24 23
16 15
8
7
0
AHB Data
PCI Data
PCI Data
PCI-to-AHB DMA,
DS = 0
