Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—USB 1.1 Device
Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
324
Order Number: 306262-004US
8.5.16.2
Receive Packet Complete (RPC)
The receive packet complete bit gets set by the UDC when an OUT packet is received.
When this bit is set, the IR14 bit in the appropriate UDC status/interrupt register is set
if receive interrupts are enabled. This bit can be used to validate the other status/error
bits in the Endpoint 14 control/status register.
The UDCCS14[RPC] bit is cleared by writing a 1 to it.
8.5.16.3
Receive Overflow (ROF)
The receive overflow bit generates an interrupt on IR14 in the appropriate UDC status/
interrupt register to alert the software that Isochronous data packets are being
dropped because neither FIFO buffer has room for them.
This bit is cleared by writing a 1 to it.
8.5.16.4
Bit 3 Reserved
Bit 3 is reserved for future use.
8.5.16.5
Bit 4 Reserved
Bit 4 is reserved for future use.
8.5.16.6
Bit 5 Reserved
Bit 5 is reserved for future use.
8.5.16.7
Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that the receive FIFO has unread data in it.
When the UDCCS14[RPC] bit is set, this bit must be read to determine if there is any
data in the FIFO that Intel XScale processor did not read.
The receive FIFO must continue to be read until this bit clears or data will be lost.
8.5.16.8
Receive Short Packet (RSP)
The receive short packet bit is used by the UDC to indicate that the received OUT
packet in the active buffer currently being read is a short packet or zero-sized packet.
This bit is updated by the UDC after the last byte is read from the active buffer and
reflects the status of the new active buffer.
If UDCCS14[RSP] is a 1 and UDCCS14[RNE] is a 0, it indicates a zero-length packet. If
a zero-length packet is present, the Intel XScale processor must not read the data
register.
UDCCS14[RSP] clears when the next OUT packet is received.
