Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
203
Intel XScale
®
Processor—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Code placed into the instruction cache should be aligned on a 1,024-byte boundary and
placed sequentially together as tightly as possible so as not to waste precious memory
space. Making the code sequential also insures even distribution across all cache ways.
Though it is possible to choose randomly located functions for cache locking, this
approach runs the risk of landing multiple cache ways in one set and few or none in
another set. This distribution unevenness can lead to excessive thrashing of the Data
and Mini Caches.
3.10.4.2
Data and Mini Cache
The IXP45X/IXP46X network processors allow the user to define memory regions
whose cache policies can be set by the user (see
policies and configurations are:
• Non Cacheable with no coalescing of memory writes.
• Non Cacheable with coalescing of memory writes.
• Mini-Data cache with write coalescing, read allocate, and write-back caching.
• Mini-Data cache with write coalescing, read allocate, and write-through caching.
• Mini-Data cache with write coalescing, read-write allocate, and write-back caching.
• Data cache with write coalescing, read allocate, and write-back caching.
• Data cache with write coalescing, read allocate, and write-through caching.
• Data cache with write coalescing, read-write allocate, and write-back caching.
To support allocating variables to these various memory regions, the tool chain
(compiler, assembler, linker and debugger), must implement named sections.
The performance of your application code depends on what cache policy you are using
for data objects. A description of when to use a particular policy is described below.
The IXP45X/IXP46X network processors allow dynamic modification of the cache
policies at run time, however, the operation is requires considerable processing time
and therefore should not be used by applications.
If the application is running under an OS, then the OS may restrict you from using
certain cache policies.
3.10.4.2.1
Non-Cacheable Regions
It is recommended that non-cache memory (X=0, C=0, and B=0) be used only if
necessary as is often necessary for I/O devices. Accessing non-cacheable memory is
likely to cause the processor to stall frequently due to the long latency of memory
reads.
3.10.4.2.2
Write-Through and Write-Back Cached Memory Regions
Write through memory regions generate more data traffic on the bus. Therefore is not
recommended that the write-through policy be used. The write back policy must be
used whenever possible.
However, in a multiprocessor environment it will be necessary to use a write through
policy if data is shared across multiple processors. In such a situation all shared
memory regions should use write through policy. Memory regions that are private to a
particular processor should use the write back policy.
