Intel ITANIUM ARCHITECTURE, Manual

Page: 96 / 604

Volume 4: Base IA-32 Instruction Reference 4:89
DEC—Decrement by 1
Description
Subtracts 1 from the operand, while preserving the state of the CF flag. The source
operand can be a register or a memory location. This instruction allows a loop counter
to be updated without disturbing the CF flag. (Use a SUB instruction with an immediate
operand of 1 to perform a decrement operation that does updates the CF flag.)
Operation
DEST

DEST - 1;
Flags Affected
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the
result.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Protected Mode Exceptions
#GP(0) If the destination is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
#SS(0) If a memory operand effective address is outside the SS segment
limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Real Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
#SS If a memory operand effective address is outside the SS segment
limit.
Opcode Instruction Description
FE /1 DEC r/m8 Decrement r/m8 by 1
FF /1 DEC r/m16 Decrement r/m16 by 1
FF /1 DEC r/m32 Decrement r/m32 by 1
48+rw DEC r16 Decrement r16 by 1
48+rd DEC r32 Decrement r32 by 1