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Volume 4: Base IA-32 Instruction Reference

4:121

FDIV/FDIVP/FIDIV—Divide

Description

Divides the destination operand by the source operand and stores the result in the 
destination location. The destination operand (dividend) is always in an FPU register; 
the source operand (divisor) can be a register or a memory location. Source operands 
in memory can be in single-real, double-real, word-integer, or short-integer formats.

The no-operand version of the instruction divides the contents of the ST(1) register by 
the contents of the ST(0) register. The one-operand version divides the contents of the 
ST(0) register by the contents of a memory location (either a real or an integer value). 
The two-operand version, divides the contents of the ST(0) register by the contents of 
the ST(

i

) register or vice versa.

The FDIVP instructions perform the additional operation of popping the FPU register 
stack after storing the result. To pop the register stack, the processor marks the ST(0) 
register as empty and increments the stack pointer (TOP) by 1. The no-operand version 
of the floating-point divide instructions always results in the register stack being 
popped. In some assemblers, the mnemonic for this instruction is FDIV rather than 
FDIVP.

The FIDIV instructions convert an integer source operand to extended-real format 
before performing the division. When the source operand is an integer 0, it is treated as 
a +0.

If an unmasked divide by zero exception (#Z) is generated, no result is stored; if the 
exception is masked, an 

 of the appropriate sign is stored in the destination operand.

The following table shows the results obtained when dividing various classes of 
numbers, assuming that neither overflow nor underflow occurs.

Opcode

Instruction

Description

D8 /6

FDIV 

m32real

Divide ST(0) by 

m32real

 and store result in ST(0)

DC /6

FDIV 

m64real

Divide ST(0) by 

m64real

 and store result in ST(0)

D8 F0+i

FDIV ST(0), ST(

i

)

Divide ST(0) by ST(

i

) and store result in ST(0)

DC F8+i

FDIV ST(i), ST(0)

Divide ST(

i

) by ST(0) and store result in ST(

i

)

DE F8+i

FDIVP ST(

i

), ST(0)

Divide ST(

i

) by ST(0), store result in ST(

i

), and pop the register 

stack

DE F9

FDIVP

Divide ST(1) by ST(0), store result in ST(1), and pop the 
register stack

DA /6

FIDIV 

m32int

Divide ST(0) by 

m32int

 and store result in ST(0)

DE /6

FIDIV 

m16int

Divide ST(0) by 

m64int

 and store result in ST(0)

Summary of Contents for ITANIUM ARCHITECTURE

Page 1: ......

Page 2: ...Intel Itanium Architecture Software Developer s Manual Volume 4 IA 32 Instruction Set Reference Revision 2 3 May 2010 Document Number 323208 ...

Page 3: ...hanges to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Intel processors based on the Itanium architec...

Page 4: ...n 4 15 2 2 3 Flags Affected 4 18 2 2 4 FPU Flags Affected 4 18 2 2 5 Protected Mode Exceptions 4 19 2 2 6 Real address Mode Exceptions 4 19 2 2 7 Virtual 8086 Mode Exceptions 4 19 2 2 8 Floating point Exceptions 4 20 2 3 IA 32 Base Instruction Reference 4 20 3 IA 32 Intel MMX Technology Instruction Reference 4 399 4 IA 32 SSE Instruction Reference 4 463 4 1 IA 32 SSE Instructions 4 463 4 2 About t...

Page 5: ... 3 17 Operation of the PSRAW Instruction 4 440 3 18 Operation of the PSRLW Instruction 4 443 3 19 Operation of the PSUBW Instruction 4 446 3 20 Operation of the PSUBSW Instruction 4 449 3 21 Operation of the PSUBUSB Instruction 4 452 3 22 High order Unpacking and Interleaving of Bytes with the PUNPCKHBW Instruction 4 455 3 23 Low order Unpacking and Interleaving of Bytes with the PUNPCKLBW Instruc...

Page 6: ...ses 4 218 2 15 LAR Descriptor Validity 4 253 2 16 LEA Address and Operand Sizes 4 258 2 17 Repeat Conditions 4 338 4 1 Real Number Notation 4 476 4 2 Denormalization Process 4 478 4 3 Results of Operations with NAN Operands 4 481 4 4 Precision and Range of SSE Datatype 4 482 4 5 Real Number and NaN Encodings 4 482 4 6 SSE Instruction Behavior with Prefixes 4 483 4 7 SIMD Integer Instructions Behav...

Page 7: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...

Page 8: ...he Itanium application architecture including application level resources programming environment and the IA 32 application interface This volume also describes optimization techniques used to generate high performance software 1 1 1 Part 1 Application Architecture Guide Chapter 1 About this Manual provides an overview of all volumes in the Intel Itanium Architecture Software Developer s Manual Ch...

Page 9: ...software 1 2 1 Part 1 System Architecture Guide Chapter 1 About this Manual provides an overview of all volumes in the Intel Itanium Architecture Software Developer s Manual Chapter 2 Intel Itanium System Environment introduces the environment designed to support execution of Itanium architecture based operating systems running IA 32 or Itanium architecture based applications Chapter 3 System Stat...

Page 10: ...ing systems need to preserve Itanium register contents and state This chapter also describes system architecture mechanisms that allow an operating system to reduce the number of registers that need to be spilled filled on interruptions system calls and context switches Chapter 5 Memory Management introduces various memory management strategies Chapter 6 Runtime Support for Control and Data Specul...

Page 11: ...2 Instruction Reference provides a detailed description of all Itanium instructions organized in alphabetical order by assembly language mnemonic Chapter 3 Pseudo Code Functions provides a table of pseudo code functions which are used to define the behavior of the Itanium instructions Chapter 4 Instruction Formats describes the encoding and instruction format instructions Chapter 5 Resource and De...

Page 12: ...itectures Software Developer s Manual Itanium System Environment The operating system environment that supports the execution of both IA 32 and Itanium architecture based code IA 32 System Environment The operating system privileged environment and resources as defined by the Intel Architecture Software Developer s Manual Resources include virtual paging control registers debugging performance mon...

Page 13: ... the Unified EFI Forum website at http www uefi org Unified Extensible Firmware Interface Specification This document defines a new model for the interface between operating systems and platform firmware 1 7 Revision History Date of Revision Revision Number Description March 2010 2 3 Added information about illegal virtualization optimization combinations and IIPA requirements Added Resource Utili...

Page 14: ...rocedures Allows IPI redirection feature to be optional Undefined behavior for 1 byte accesses to the non architected regions in the IPI block Modified insertion behavior for TR overlaps See Vol 2 Part I Ch 4 for details Bus parking feature is now optional for PAL_BUS_GET_FEATURES Introduced low power synchronization primitive using hint instruction FR32 127 is now preserved in PAL calling convent...

Page 15: ...n 2 2 and 3 Part I Volume 3 Added Performance Counter Standardization Sections 7 2 3 and 11 6 Part I Volume 2 Added Freeze Bit Functionality in Context Switching and Interrupt Generation Clarification Sections 7 2 1 7 2 2 7 2 4 1 and 7 2 4 2 Part I Volume 2 Added IA_32_Exception Debug IIPA Description Change Section 9 2 Part I Volume 2 Added capability for Allowing Multiple PAL_A_SPEC and PAL_B En...

Page 16: ...S changes extend calls to allow implementation specific feature control Section 11 8 3 Split PAL_A architecture changes Section 11 1 6 Simple barrier synchronization clarification Section 13 4 2 Limited speculation clarification added hardware generated speculative references Section 4 4 6 PAL memory accesses and restrictions clarification Section 11 9 PSP validity on INITs from PAL_MC_ERROR_INFO ...

Page 17: ...plify the call to provide more information regarding machine check Chapter 11 PAL_ENTER_IA_32_Env call changes entry parameter represents the entry order SAL needs to initialize all the IA 32 registers properly before making this call Chapter 11 PAL_CACHE_FLUSH added a new cache_type argument Chapter 11 PAL_SHUTDOWN removed from list of PAL calls Chapter 11 Clarified memory ordering changes Chapte...

Page 18: ...registers by IA 32 instructions see the state of the Itanium registers defined to hold the IA 32 state after entering the IA 32 instruction set State mappings IA 32 numeric instructions are controlled by and reflect their status in FCW FSW FTW FCS FIP FOP FDS and FEA On exit from the IA 32 instruction set Itanium numeric status and control resources defined to hold IA 32 state reflect the results ...

Page 19: ... operands from the IA 32 instruction set including MMX technology and SSE instructions Nested TLB fault Alternative data TLB fault VHPT data fault Data TLB fault Data Page Not Present fault Data NaT Page Consumption Abort Data Key Miss fault Data Key Permission fault Data Access Rights fault Data Dirty bit fault Data Access bit fault 2 2 Interpreting the IA 32 Instruction Reference Pages This sect...

Page 20: ...byte first rb rw rd A register code from 0 through 7 added to the hexadecimal byte given at the left of the plus sign to form a single opcode byte The register codes are given in Table 2 1 i A number used in floating point instructions when one of the operands is ST i from the FPU register stack The number i which can range from 0 to 7 is added to the hexadecimal byte given at the left of the plus...

Page 21: ...ster AL BL CL DL AH BH CH and DH or a byte from memory r m16 A word general purpose register or memory operand used for instructions whose operand size attribute is 16 bits The word general purpose registers are AX BX CX DX SP BP SI and DI The contents of memory are found at the address provided by the effective address computation r m32 A doubleword general purpose register or memory operand used...

Page 22: ... 0 through 7 mm An MMX technology register The 64 bit MMX technology registers are MM0 through MM7 mm m32 The low order 32 bits of an MMX technology register or a 32 bit memory operand The 64 bit MMX technology registers are MM0 through MM7 The contents of memory are found at the address provided by the effective address computation mm m64 An MMX technology register or a 64 bit memory operand The ...

Page 23: ...y by the number of bits indicated by the count operand The following identifiers are used in the algorithmic descriptions OperandSize and AddressSize The OperandSize identifier represents the operand size attribute of the instruction which is either 16 or 32 bits The AddressSize identifier represents the address size attribute which is either 16 or 32 bits For example the following pseudo code ind...

Page 24: ...ts the result of an operation as a signed 16 bit value If the result is less than 32768 it is represented by the saturated value 32768 8000H if it is greater than 32767 it is represented by the saturated value 32767 7FFFH SaturateToUnsignedByte Represents the result of an operation as a signed 8 bit value If the result is less than zero it is represented by the saturated value zero 00H if it is gr...

Page 25: ... by the instruction When a flag is cleared it is equal to 0 when it is set it is equal to 1 The arithmetic and logical instructions usually assign values to the status flags in a uniform manner see Appendix A EFLAGS Cross Reference in the Intel Architecture Software Developer s Manual Volume 1 Non conventional assignments are described in the Operation section The values of flags listed as undefin...

Page 26: ... lists the exceptions that can occur when the instruction is executed in virtual 8086 mode Table 2 2 Exception Mnemonics Names and Vector Numbers Vector No Mnemonic Name Source 0 DE Divide Error DIV and IDIV instructions 1 DB Debug Any code or data reference 3 BP Breakpoint INT 3 instruction 4 OF Overflow INTO instruction 5 BR BOUND Range Exceeded BOUND instruction 6 UD Invalid Opcode Undefined Op...

Page 27: ...description of these exceptions 2 3 IA 32 Base Instruction Reference The remainder of this chapter provides detailed descriptions of each of the Intel architecture instructions Table 2 3 Floating point Exception Mnemonics and Names Vector No Mnemonic Name Source 16 IS IA Floating point invalid operation Stack overflow or underflow Invalid arithmetic operation FPU stack overflow or underflow Invali...

Page 28: ... the addition produces a decimal carry the AH register is incremented by 1 and the CF and AF flags are set If there was no decimal carry the CF and AF flags are cleared and the AH register is unchanged In either case bits 4 through 7 of the AL register are cleared to 0 Operation IF AL AND FH 9 OR AF 1 THEN AL AL 6 AH AH 1 AF 1 CF 1 ELSE AF 0 CF 0 FI AL AL AND FH Flags Affected The AF and CF flags ...

Page 29: ... and then clears the AH register to 00H The value in the AX register is then equal to the binary equivalent of the original unpacked two digit number in registers AH and AL Operation tempAL AL tempAH AH AL tempAL tempAH imm8 AND FFH AH 0 The immediate value imm8 is taken from the second byte of the instruction which under normal assembly is 0AH 10 decimal However this immediate value can be change...

Page 30: ... instruction then adjusts the contents of the AX register to contain the correct 2 digit unpacked BCD result Operation tempAL AL AH tempAL imm8 AL tempAL MOD imm8 The immediate value imm8 is taken from the second byte of the instruction which under normal assembly is 0AH 10 decimal However this immediate value can be changed to produce a different result Flags Affected The SF ZF and PF flags are s...

Page 31: ... digit unpacked BCD result If the subtraction produced a decimal carry the AH register is decremented by 1 and the CF and AF flags are set If no decimal carry occurred the CF and AF flags are cleared and the AH register is unchanged In either case the AL register is left with its top nibble set to 0 Operation IF AL AND FH 9 OR AF 1 THEN AL AL 6 AH AH 1 AF 1 CF 1 ELSE CF 0 AF 0 FI AL AL AND FH Flag...

Page 32: ...EST SRC CF Flags Affected The OF SF ZF AF CF and PF flags are set according to the result Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Ri...

Page 33: ... page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address ...

Page 34: ...F and PF flags are set according to the result Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty...

Page 35: ...fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is out...

Page 36: ...Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination operand points to a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effe...

Page 37: ...a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignm...

Page 38: ...system by an application program to match the privilege level of the application program Here the segment selector passed to the operating system is placed in the destination operand and segment selector for the application program s code segment is placed in the source operand The RPL field in the source operand represents the privilege level of the application program Execution of the ARPL instr...

Page 39: ...d Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is...

Page 40: ...instruction The bounds limit data structure two words or doublewords containing the lower and upper limits of the array is usually placed just before the array itself making the limits addressable via a constant offset from the beginning of the array Because the address of the array already will be present in a register this practice avoids extra bus cycles to obtain the effective address of the a...

Page 41: ...f alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions BR If the bounds test fails GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions BR If the bounds test fails GP 0 If a me...

Page 42: ...SRC 0 THEN ZF 1 DEST is undefined ELSE ZF 0 temp 0 WHILE Bit SRC temp 0 DO temp temp 1 DEST temp OD FI Flags Affected The ZF flag is set to 1 if all the source operand is 0 otherwise the ZF flag is cleared The CF OF SF AF and PF flags are undefined Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault D...

Page 43: ...ng is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment li...

Page 44: ...HEN ZF 1 DEST is undefined ELSE ZF 0 temp OperandSize 1 WHILE Bit SRC temp 0 DO temp temp 1 DEST temp OD FI Flags Affected The ZF flag is set to 1 if all the source operand is 0 otherwise the ZF flag is cleared The CF OF SF AF and PF flags are undefined Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fa...

Page 45: ...ng is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment li...

Page 46: ...lt is undefined Operation TEMP DEST DEST 7 0 TEMP 31 24 DEST 15 8 TEMP 23 16 DEST 23 16 TEMP 15 8 DEST 31 24 TEMP 7 0 Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Exceptions All Operating Modes None Intel Architecture Compatibility Information The BSWAP instruction is not supported on Intel architecture processors earlier th...

Page 47: ... bit offset are stored in the immediate bit offset field and the high order bits are shifted and combined with the byte displacement in the addressing mode by the assembler The processor will ignore the high order bits if they are not zero When accessing a bit in memory the processor may access 4 bytes starting from the memory address for a 32 bit operand size using by the following relationship E...

Page 48: ...register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a me...

Page 49: ... 0 to 31 for an immediate offset Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand See BT Bit Test on page 4 40 for more information on this addressing mechanism Operation CF Bit BitBase BitOffset Bit BitBase BitOffset NOT Bit BitBase BitOffset Flags Affected The CF flag contains the...

Page 50: ...lt occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outsid...

Page 51: ... a register offset and 0 to 31 for an immediate offset Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand See BT Bit Test on page 4 40 for more information on this addressing mechanism Operation CF Bit BitBase BitOffset Bit BitBase BitOffset 0 Flags Affected The CF flag contains the v...

Page 52: ...occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside t...

Page 53: ... for a register offset and 0 to 31 for an immediate offset Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand See BT Bit Test on page 4 40 for more information on this addressing mechanism Operation CF Bit BitBase BitOffset Bit BitBase BitOffset 1 Flags Affected The CF flag contains t...

Page 54: ... occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP If a memory operand effective address is outside th...

Page 55: ...tion When executing a near call the processor pushes the value of the EIP register which contains the address of the instruction following the CALL instruction onto the procedure stack for use later as a return instruction pointer The processor then jumps to the address specified with the target operand for the called procedure The target operand specifies either an absolute address in the code se...

Page 56: ...be pushed on the stack When the processor is operating in protected mode a far call can also be used to access a code segment at a different privilege level or to switch tasks Here the processor uses the segment selector part of the far address to access the segment descriptor for the segment being jumped to Depending on the value of the type and access rights information in the segment selector t...

Page 57: ...T is rel32 ELSE OperandSize 16 IF stack not large enough for a 2 byte return address THEN SS 0 FI Push IP EIP EIP DEST AND 0000FFFFH DEST is rel16 FI FI ELSE near absolute call IF the instruction pointer is not within code segment limit THEN GP 0 FI IF OperandSize 32 THEN IF stack not large enough for a 4 byte return address THEN SS 0 FI Push EIP EIP DEST DEST is r m32 ELSE OperandSize 16 IF stack...

Page 58: ...NG CODE SEGMENT GO TO CALL GATE GO TO TASK GATE GO TO TASK STATE SEGMENT FI CONFORMING CODE SEGMENT IF DPL CPL THEN GP new code segment selector FI IF not present THEN NP selector FI IF OperandSize 32 THEN IF stack not large enough for a 6 byte return address THEN SS 0 FI IF the instruction pointer is not within code segment limit THEN GP 0 FI Push CS padded with 16 high order bits Push EIP CS DES...

Page 59: ...ate DPL CPL or RPL THEN GP call gate selector FI IF not present THEN NP call gate selector FI IF Itanium System Environment THEN IA 32_Intercept Gate CALL IF call gate code segment selector is null THEN GP 0 FI IF call gate code segment selector index is outside descriptor table limits THEN GP code segment selector FI Read code segment descriptor IF code segment segment descriptor does not indicat...

Page 60: ...N GP 0 FI SS newSS segment descriptor information also loaded ESP newESP CS EIP CallGate CS InstructionPointer segment descriptor information also loaded Push oldSS oldESP from calling procedure temp parameter count from call gate masked to 5 bits Push parameters from calling procedure s stack temp Push oldCS oldEIP return address to calling procedure ELSE CallGateSize 16 IF stack does not have ro...

Page 61: ... selector FI IF Itanium System Environment THEN IA 32_Intercept Gate CALL Read the TSS segment selector in the task gate descriptor IF TSS segment selector local global bit is set to local OR index not within GDT limits THEN GP TSS selector FI Access TSS descriptor in GDT IF TSS descriptor specifies that the TSS is busy low order 5 bits set to 00001 THEN GP TSS selector FI IF TSS not present THEN ...

Page 62: ...gment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector GP selector If code segment or gate or TSS selector index is outside descriptor table limits If the segment descriptor pointed to by the segment selector in the destination operand is not for a conforming code segment nonconforming code segment call gate task gate or task state segment If th...

Page 63: ...and ESP are beyond the end of the TSS If the new stack segment selector is null If the RPL of the new stack segment selector in the TSS is not equal to the DPL of the code segment being accessed If DPL of the stack segment descriptor for the new stack segment is not equal to the DPL of the code segment descriptor If the new stack segment is not a writable data segment If segment selector index for...

Page 64: ...may force the operand size to 16 when CBW is used and to 32 when CWDE is used Others may treat these mnemonics as synonyms CBW CWDE and use the current setting of the operand size attribute to determine the size of values to be converted regardless of the mnemonic used The CWDE instruction is different from the CWD convert word to double instruction The CWD instruction uses the DX AX register pair...

Page 65: ...4 58 Volume 4 Base IA 32 Instruction Reference CDQ Convert Double to Quad See entry for CWD CDQ Convert Word to Double Convert Double to Quad ...

Page 66: ...r Carry Flag Description Clears the CF flag in the EFLAGS register Operation CF 0 Flags Affected The CF flag is cleared to 0 The OF ZF SF AF and PF flags are unaffected Exceptions All Operating Modes None Opcode Instruction Description F8 CLC Clear CF flag ...

Page 67: ...n the EFLAGS register When the DF flag is set to 0 string operations increment the index registers ESI and or EDI Operation DF 0 Flags Affected The DF flag is cleared to 0 The CF OF ZF SF AF and PF flags are unaffected Exceptions All Operating Modes None Opcode Instruction Description FC CLD Clear DF flag ...

Page 68: ...he following decision table indicates the action of the CLI instruction bottom of the table depending on the processor s mode of operating and the CPL and IOPL of the currently running program or procedure top of the table Notes XDon t care NAction in column 1 not taken YAction in column 1 taken Operation OLD_IF IF IF PE 0 Executing in real address mode THEN IF 0 ELSE IF VM 0 Executing in protecte...

Page 69: ... cleared to 0 if the CPL is equal to or less than the IOPL otherwise the it is not affected The other flags in the EFLAGS register are unaffected Additional Itanium System Environment Exceptions IA 32_Intercept System Flag Intercept Trap if CFLG ii is 1 and the IF flag changes state Protected Mode Exceptions GP 0 If the CPL is greater has less privilege than the IOPL of the current program or proc...

Page 70: ...to synchronize the saving of FPU context in multitasking applications See the description of the TS flag in the Intel Architecture Software Developer s Manual Volume 3 for more information about this flag Operation IF Itanium System Environment THEN IA 32_Intercept INST CLTS CR0 TS 0 Flags Affected The TS flag in CR0 register is cleared Additional Itanium System Environment Exceptions IA 32_Interc...

Page 71: ...tion Complements the CF flag in the EFLAGS register Operation CF NOT CF Flags Affected The CF flag contains the complement of its original value The OF ZF SF AF and PF flags are unaffected Exceptions All Operating Modes None Opcode Instruction Description F5 CMC Complement CF flag ...

Page 72: ... Move if less or equal ZF 1 or SF OF 0F 4E cw cd CMOVLE r32 r m32 Move if less or equal ZF 1 or SF OF 0F 46 cw cd CMOVNA r16 r m16 Move if not above CF 1 or ZF 1 0F 46 cw cd CMOVNA r32 r m32 Move if not above CF 1 or ZF 1 0F 42 cw cd CMOVNAE r16 r m16 Move if not above or equal CF 1 0F 42 cw cd CMOVNAE r32 r m32 Move if not above or equal CF 1 0F 43 cw cd CMOVNB r16 r m16 Move if not below CF 0 0F...

Page 73: ...d below are used for unsigned integers Because a particular state of the status flags can sometimes be interpreted in two ways two mnemonics are defined for some opcodes For example the CMOVA conditional move if above instruction and the CMOVNBE conditional move if not below or equal instruction are alternate mnemonics for the opcode 0F 47H Opcode Instruction Description 0F 41 cw cd CMOVNO r16 r m...

Page 74: ...Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a ...

Page 75: ...ode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 76: ...CF OF SF ZF AF and PF flags are set according to the result Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fau...

Page 77: ...king is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment ...

Page 78: ...ting of the DF flag in the EFLAGS register If the DF flag is 0 the ESI and EDI register are incremented if the DF flag is 1 the ESI and EDI registers are decremented The registers are incremented or decremented by 1 for byte operations by 2 for word operations or by 4 for doubleword operations The CMPS CMPSB CMPSW and CMPSD instructions can be preceded by the REP prefix for block comparisons of EC...

Page 79: ...ed TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment se...

Page 80: ...rtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 81: ...s a locked read without also producing a locked write Operation accumulator AL AX or EAX depending on whether a byte word or doubleword comparison is being performed IF Itanium System Environment AND External_Atomic_Lock_Required AND DCR lc THEN IA 32_Intercept LOCK CMPXCHG IF accumulator DEST THEN ZF 1 DEST SRC ELSE ZF 0 accumulator DEST FI Flags Affected The ZF flag is set if the values in the d...

Page 82: ...writable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Rea...

Page 83: ...locked write Operation IF Itanium System Environment AND External_Atomic_Lock_Required AND DCR lc THEN IA 32_Intercept LOCK CMPXCHG IF EDX EAX DEST ZF 1 DEST ECX EBX ELSE ZF 0 EDX EAX DEST FI Flags Affected The ZF flag is set if the destination operand and EDX EAX are equal otherwise it is cleared The CF PF AF SF and OF flags are unaffected Additional Itanium System Environment Exceptions Itanium ...

Page 84: ...cking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment...

Page 85: ...gister is 80000000H the processor returns the highest value the CPUID instruction recognizes in the EAX register for returning extended function information Always use an EAX parameter value that is equal to or greater than zero and less than or equal to this highest EAX return value for extended function information The CPUID instruction can be executed at any privilege level to serialize instruc...

Page 86: ...ssors Extended Function CPUID Information 8000000H EAX EBX ECX EDX Maximum Input Value for Extended Function CPUID Information Reserved Reserved Reserved 8000001H EAX EBX ECX EDX Extended Processor Signature and Extended Feature Bits Currently reserved Reserved Reserved Reserved 8000002H EAX EBX ECX EDX Processor Brand String Processor Brand String Continued Processor Brand String Continued Proces...

Page 87: ... instruction in addition to loading the processor signature in the EAX register loads the EDX register with the feature flags The feature flags when a Flag 1 indicate what features the processor supports Table 2 5 lists the currently defined feature flag values A feature flag set to 1 indicates the corresponding feature is supported Software should identify Intel as the vendor to properly interpre...

Page 88: ... 13 PGE PTE Global Bit The global bit in page directory entries PDEs and page table entries PTEs is supported indicating TLB entries that are common to different processes and need not be flushed The CR4 PGE bit controls this feature 14 MCA Machine Check Architecture The Machine Check Architecture which provides a compatible mechanism for error reporting is supported The MCG_CAP MSR contains featu...

Page 89: ...e supported for fast save and restore of the floating point context Presence of this bit also indicates that CR4 OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions 25 SSE SSE The processor supports the SSE extensions 26 SSE2 SSE2 The processor supports the SSE2 extensions 27 SS Self Snoop The processor supports the management of conflicting...

Page 90: ...6 23 Number of logical processors per physical processor EBX 31 24 Initial APIC ID Reserved for processors based on Itanium architecture ECX Reserved EDX Feature flags BREAK EAX 2H EAX Cache and TLB information EBX Cache and TLB information ECX Cache and TLB information EDX Cache and TLB information BREAK EAX 80000000H EAX Highest extended function input value understood by CPUID EBX Reserved ECX ...

Page 91: ..._serialize Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Exceptions All Operating Modes None Intel Architecture Compatibility The CPUID instruction is not supported in early models of the Intel486 processor or in any Intel architecture processor earlier than the Intel486 processor The ID flag in the EFLAGS register can be use...

Page 92: ...end from a doubleword before doubleword division The CWD and CDQ mnemonics reference the same opcode The CWD instruction is intended for use when the operand size attribute is 16 and the CDQ instruction for when the operand size attribute is 32 Some assemblers may force the operand size to 16 when CWD is used and to 32 when CDQ is used Others may treat these mnemonics as synonyms CWD CDQ and use t...

Page 93: ...4 86 Volume 4 Base IA 32 Instruction Reference CWDE Convert Word to Doubleword See entry for CBW CWDE Convert Byte to Word Convert Word to Doubleword ...

Page 94: ... IF AL AND 0FH 9 or AF 1 THEN AL AL 6 CF CF OR CarryFromLastAddition CF OR carry from AL AL 6 AF 1 ELSE AF 0 FI IF AL AND F0H 90H or CF 1 THEN AL AL 60H CF 1 ELSE CF 0 FI Example ADD AL BL Before AL 79H BL 35H EFLAGS OSZAPC XXXXXX After AL AEH BL 35H EFLAGS 0SZAPC 110000 DAA Before AL 79H BL 35H EFLAGS OSZAPC 110000 After AL AEH BL 35H EFLAGS 0SZAPC X00111 Flags Affected The CF and AF flags are se...

Page 95: ... accordingly Operation IF AL AND 0FH 9 OR AF 1 THEN AL AL 6 CF CF OR BorrowFromLastSubtraction CF OR borrow from AL AL 6 AF 1 ELSE AF 0 FI IF AL 9FH or CF 1 THEN AL AL 60H CF 1 ELSE CF 0 FI Example SUB AL BL Before AL 35H BL 47H EFLAGS OSZAPC XXXXXX After AL EEH BL 47H EFLAGS 0SZAPC 010111 DAA Before AL EEH BL 47H EFLAGS OSZAPC 010111 After AL 88H BL 47H EFLAGS 0SZAPC X10111 Flags Affected The CF ...

Page 96: ...Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is...

Page 97: ...e Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 98: ...on rather than with the CF flag Operation IF SRC 0 THEN DE divide error FI IF OpernadSize 8 word byte operation THEN temp AX SRC IF temp FFH THEN DE divide error ELSE AL temp AH AX MOD SRC FI ELSE IF OpernadSize 16 doubleword word operation THEN temp DX AX SRC IF temp FFFFH THEN DE divide error ELSE AX temp DX DX AX MOD SRC FI Opcode Instruction Description F6 6 DIV r m8 Unsigned divide AX by r m8...

Page 99: ... Fault Data Dirty Bit Fault Protected Mode Exceptions DE If the source operand divisor is 0 If the quotient is too large for the designated register GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a pag...

Page 100: ...is 0 If the quotient is too large for the designated register GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 101: ...frame for an already called procedure An ENTER instruction is commonly followed by a CALL JMP or Jcc instruction to transfer program control to the procedure being called If the nesting level is 0 the processor pushes the frame pointer from the EBP register onto the stack copies the current stack pointer from the ESP register into the EBP register and loads the ESP register with the current stack ...

Page 102: ... doubleword push ELSE OperandSize 16 Push FrameTemp word push FI GOTO CONTINUE FI CONTINUE IF StackSize 32 THEN EBP FrameTemp ESP EBP Size ELSE StackSize 16 BP FrameTemp SP BP Size FI END Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Da...

Page 103: ...Stack Frame for Procedure Parameters Continued Protected Mode Exceptions SS 0 If the new value of the SP or ESP register is outside the stack segment limit PF fault code If a page fault occurs Real Address Mode Exceptions None Virtual 8086 Mode Exceptions None ...

Page 104: ...onentiated using the following formula xy 2 y log 2 x Operation ST 0 2ST 0 1 FPU Flags Affected C1 Set to 0 if stack underflow occurred Indicates rounding direction if the inexact result exception P is generated 0 not roundup 1 roundup C0 C2 C3 Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Flo...

Page 105: ... IA 32 Instruction Reference F2XM1 Compute 2x 1 Continued Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 106: ...f stack underflow occurred otherwise cleared to 0 C0 C2 C3 Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Floating point Exceptions IS Stack underflow occurred Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions...

Page 107: ...ng popped In some assemblers the mnemonic for this instruction is FADD rather than FADDP The FIADD instructions convert an integer source operand to extended real format before performing the addition The table on the following page shows the results obtained when adding various classes of numbers assuming that neither overflow nor underflow occurs When the sum of two operands with opposite signs ...

Page 108: ...if the inexact result exception P is generated 0 not roundup 1 roundup C0 C2 C3 Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fau...

Page 109: ...ory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective addres...

Page 110: ...em Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode E...

Page 111: ... operand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned mem...

Page 112: ...memory The following table shows the results obtained when storing various classes of numbers in packed BCD format Notes Fmeans finite real number Dmeans packed BCD number indicates floating point invalid operation IA exception 0 or 1 depending on the rounding mode If the source value is too large for the destination format and the invalid operation exception is not masked an invalid operation exc...

Page 113: ...Source operand is empty contains a NaN or unsupported format or contains value that exceeds 18 BCD digits in length P Value cannot be represented exactly in destination format Protected Mode Exceptions GP 0 If a segment register is being loaded with a segment selector that points to a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS...

Page 114: ...ptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 115: ...nBit ST 0 FPU Flags Affected C1 Set to 0 if stack underflow occurred otherwise cleared to 0 C0 C2 C3 Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Floating point Exceptions IS Stack underflow occurred Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS ...

Page 116: ...OE ZE DE IE ES SF and B flags in the FPU status word are cleared The C0 C1 C2 and C3 flags are undefined Floating point Exceptions None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mo...

Page 117: ...mation with the CPUID instruction see CPUID CPU Identification on page 4 78 If both the CMOV and FPU feature bits are set the FCMOVcc instructions are supported Operation IF condition TRUE ST 0 ST i FI FPU Flags Affected C1 Set to 0 if stack underflow occurred C0 C2 C3 Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Regis...

Page 118: ...on Reference 4 111 FCMOVcc Floating point Conditional Move Continued Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 119: ...ssor marks the ST 0 register as empty and increments the stack pointer TOP by 1 The FCOM instructions perform the same operation as the FUCOM instructions The only difference is how they handle QNaN operands The FCOM instructions raise an invalid arithmetic operand exception IA when either or both of the operands is a NaN value or is in an unsupported format The FUCOM instructions perform the same...

Page 120: ...ed otherwise cleared to 0 C0 C2 C3 See table on previous page Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault...

Page 121: ...nabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES ...

Page 122: ... generate an invalid arithmetic operand exception for QNaNs If invalid operation exception is unmasked the status flags are not set if the invalid arithmetic operand exception is generated The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation To pop the register stack the processor marks the ST 0 register as empty and increments the stack pointer TOP by...

Page 123: ... ZF PF CF 111 FI FI FI IF instruction is FUCOMI or FUCOMIP THEN IF ST 0 or ST i QNaN but not SNaN or unsupported format THEN ZF PF CF 111 ELSE ST 0 or ST i is SNaN or unsupported format IA IF FPUControlWord IM 1 THEN ZF PF CF 111 FI FI FI IF instruction is FCOMIP or FUCOMIP THEN PopRegisterStack FI FPU Flags Affected C1 Set to 0 if stack underflow occurred otherwise cleared to 0 C0 C2 C3 Not affec...

Page 124: ...ne or both operands are NaN values or have unsupported formats FUCOMI or FUCOMIP instruction One or both operands are SNaN values but not QNaNs or have undefined formats Detection of a QNaN value does not raise an invalid operand exception Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is se...

Page 125: ...ource operand is outside the acceptable range the C2 flag in the FPU status word is set and the value in register ST 0 remains unchanged The instruction does not raise an exception when the source operand is out of range It is up to the program to check the C2 flag for out of range conditions Source values outside the range 263 to 263 can be reduced to the range of the instruction by subtracting a...

Page 126: ...d Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Floating point Exceptions IS Stack underflow occurred IA Source operand is an SNaN value or unsupported format D Result is a denormal value U Result is too small for destination format P Value cannot be represented exactly in destination format Protected M...

Page 127: ...lags Affected The C1 flag is set to 0 otherwise cleared to 0 The C0 C2 and C3 flags are undefined Floating point Exceptions None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exce...

Page 128: ...the floating point divide instructions always results in the register stack being popped In some assemblers the mnemonic for this instruction is FDIV rather than FDIVP The FIDIV instructions convert an integer source operand to extended real format before performing the division When the source operand is an integer 0 it is treated as a 0 If an unmasked divide by zero exception Z is generated no r...

Page 129: ...struction is FIDIV THEN DEST DEST ConvertExtendedReal SRC ELSE source operand is real number DEST DEST SRC FI FI IF instruction FDIVP THEN PopRegisterStack FI FPU Flags Affected C1 Set to 0 if stack underflow occurred Indicates rounding direction if the inexact result exception P is generated 0 not roundup 1 roundup C0 C2 C3 Undefined DEST F 0 0 F NaN 0 0 0 0 NaN F F 0 0 F NaN I F 0 0 F NaN SRC 0 ...

Page 130: ...ation format Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory referen...

Page 131: ... marks the ST 0 register as empty and increments the stack pointer TOP by 1 The no operand version of the floating point divide instructions always results in the register stack being popped In some assemblers the mnemonic for this instruction is FDIVR rather than FDIVRP The FIDIVR instructions convert an integer source operand to extended real format before performing the division If an unmasked ...

Page 132: ...Operation IF DEST 0 THEN Z ELSE IF instruction is FIDIVR THEN DEST ConvertExtendedReal SRC DEST ELSE source operand is real number DEST SRC DEST FI FI IF instruction FDIVRP THEN PopRegisterStack FI FPU Flags Affected C1 Set to 0 if stack underflow occurred Indicates rounding direction if the inexact result exception P is generated 0 not roundup 1 roundup C0 C2 C3 Undefined DEST F 0 0 F NaN NaN SRC...

Page 133: ...estination format Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory re...

Page 134: ...ted Operation TAG i 11B FPU Flags Affected C0 C1 C2 C3 undefined Floating point Exceptions None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set Opcode Instruction Description ...

Page 135: ...0 The FICOMP instructions pop the register stack following the comparison To pop the register stack the processor marks the ST 0 register empty and increments the stack pointer TOP by 1 Operation CASE relation of operands OF ST 0 SRC C3 C2 C0 000 ST 0 SRC C3 C2 C0 001 ST 0 SRC C3 C2 C0 100 Unordered C3 C2 C0 111 ESAC IF instruction FICOMP THEN PopRegisterStack FI FPU Flags Affected C1 Set to 0 if ...

Page 136: ...ess is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions...

Page 137: ...Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Floating point Exceptions IS Stack overflow occurred Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register c...

Page 138: ...nd effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory re...

Page 139: ... marked empty Operation IF TOP 7 THEN TOP 0 ELSE TOP TOP 1 FI FPU Flags Affected The C1 flag is set to 0 otherwise generates an IS fault The C0 C2 and C3 flags are undefined Floating point Exceptions IS Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM...

Page 140: ...ting point exceptions before performing the initialization the FNINIT instruction does not Operation FPUControlWord 037FH FPUStatusWord 0 FPUTagWord FFFFH FPUDataPointer 0 FPUInstructionPointer 0 FPULastInstructionOpcode 0 FPU Flags Affected C0 C1 C2 C3 cleared to 0 Floating point Exceptions None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR ...

Page 141: ...l number Imeans integer indicates floating point invalid operation IA exception 0 or 1 depending on the rounding mode If the source value is a non integral value it is rounded to an integer value according to the rounding mode specified by the RC field of the FPU control word If the value being stored is too large for the destination format is an is a NaN or is in an unsupported format and if the ...

Page 142: ...ey Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Floating point Exceptions IS Stack underflow occurred IA Source operand is too large for the destination format Source operand is a NaN value or unsupported format P Value cannot be represented exactly in destination format Protected Mode Exceptions GP 0 If the destination is located in a no...

Page 143: ...erand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory...

Page 144: ...em Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Floating point E...

Page 145: ...s AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective...

Page 146: ...ANT FPU Flags Affected C1 Set to 1 if stack overflow occurred otherwise cleared to 0 C0 C2 C3 Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Floating point Exceptions IS Stack overflow occurred Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Opcode Instruction Descri...

Page 147: ...FLDLN2 FLDZ Load Constant Continued Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set Intel Architecture Compatibility Information When the RC field is set to round to nearest the FPU produces the same constants that is produced by the Intel 8087 and Intel287 math coprocessors ...

Page 148: ...ight unmask a pending exception in the FPU status word That exception is then generated upon execution of the next waiting floating point instruction Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consum...

Page 149: ...erand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory...

Page 150: ...ception will be generated upon execution of the next floating point instruction except for the no wait floating point instructions To avoid generating exceptions when loading a new environment clear all the exception flags in the FPU status word that is being loaded Operation FPUControlWord SRC FPUControlWord FPUStatusWord SRC FPUStatusWord FPUTagWord SRC FPUTagWord FPUDataPointer SRC FPUDataPoint...

Page 151: ... checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside...

Page 152: ...the floating point multiply instructions always results in the register stack being popped In some assemblers the mnemonic for this instruction is FMUL rather than FMULP The FIMUL instructions convert an integer source operand to extended real format before performing the multiplication The sign of the result is always the exclusive OR of the source signs even if one or more of the values being mu...

Page 153: ...occurred Indicates rounding direction if the inexact result exception P fault is generated 0 not roundup 1 roundup C0 C2 C3 Undefined Floating point Exceptions IS Stack underflow occurred IA Operand is an SNaN value or unsupported format One operand is 0 and the other is D Source operand is a denormal value U Result is too small for destination format O Result is too large for destination format P...

Page 154: ... memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES F...

Page 155: ...P register FPU Flags Affected C0 C1 C2 C3 undefined Floating point Exceptions None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set Opcode Instruction Description D9 D0 FNOP No...

Page 156: ...restriction on the range of source operands that FPATAN can accept Operation ST 1 arctan ST 1 ST 0 PopRegisterStack FPU Flags Affected C1 Set to 0 if stack underflow occurred Indicates rounding direction if the inexact result exception P is generated 0 not roundup 1 roundup C0 C2 C3 Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl ...

Page 157: ...U Result is too small for destination format P Value cannot be represented exactly in destination format Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set Intel Architecture Compatibility Information The source operands for this instruction are restricted for the 80287 math coprocessor t...

Page 158: ...ollowing table shows the results obtained when computing the remainder of various classes of numbers assuming that underflow does not occur Notes Fmeans finite real number indicates floating point invalid arithmetic operand IA exception indicates floating point zero divide Z exception When the result is 0 its sign is the same as that of the dividend When the modulus is the result is equal to the v...

Page 159: ...h in between the instructions in the loop An important use of the FPREM instruction is to reduce the arguments of periodic functions When reduction is complete the instruction stores the three least significant bits of the quotient in the C3 C1 and C0 flags of the FPU status word This information is important in argument reduction for the tangent function using a modulus of 4 because it locates th...

Page 160: ...urred IA Source operand is an SNaN value modulus is 0 dividend is or unsupported format D Source operand is a denormal value U Result is too small for destination format Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 161: ...ntrol has no effect The following table shows the results obtained when computing the remainder of various classes of numbers assuming that underflow does not occur Notes Fmeans finite real number indicates floating point invalid arithmetic operand IA exception indicates floating point zero divide Z exception When the result is 0 its sign is the same as that of the dividend When the modulus is the...

Page 162: ...An important use of the FPREM1 instruction is to reduce the arguments of periodic functions When reduction is complete the instruction stores the three least significant bits of the quotient in the C3 C1 and C0 flags of the FPU status word This information is important in argument reduction for the tangent function using a modulus of 4 because it locates the original angle in the correct one of ei...

Page 163: ...ed IA Source operand is an SNaN value modulus divisor is 0 dividend is or unsupported format D Source operand is a denormal value U Result is too small for destination format Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 164: ...and is out of range It is up to the program to check the C2 flag for out of range conditions Source values outside the range 263 to 263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2 or by using the FPREM instruction with a divisor of 2 The value 1 0 is pushed onto the register stack after the tangent has been computed to maintain compatibility w...

Page 165: ... Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Floating point Exceptions IS Stack underflow occurred IA Source operand is an SNaN value or unsupported format D Source operand is a denormal value U Result is too small for destination format P Value cannot be represented exactly in destination f...

Page 166: ...tack underflow occurred Indicates rounding direction if the inexact result exception P is generated 0 not roundup 1 roundup C0 C2 C3 Undefined Floating point Exceptions IS Stack underflow occurred IA Source operand is an SNaN value or unsupported format D Source operand is a denormal value P Source operand is not an integral value Additional Itanium System Environment Exceptions Itanium Reg Faults...

Page 167: ...ruction should be executed in the same operating mode as the corresponding FSAVE FNSAVE instruction If one or more unmasked exception bits are set in the new FPU status word a floating point exception will be generated To avoid raising exceptions when loading a new operating environment clear all the exception flags in the FPU status word that is being loaded Operation FPUControlWord SRC FPUContro...

Page 168: ...ontains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment ...

Page 169: ...VE instruction in the instruction stream have been executed After the FPU state has been saved the FPU is reset to the same default values it is set to with the FINIT FNINIT instructions see FINIT FNINIT Initialize Floating point Unit on page 4 133 The FSAVE FNSAVE instructions are typically used when the operating system needs to perform a context switch an exception handler needs to use the FPU ...

Page 170: ...mission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside t...

Page 171: ...limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made Intel Architecture Compatibility Information For Intel math coprocessors and FPUs prior to the Pentium processor an FWAIT instruction should be executed before attempting to read from the memory image stored with a prior FSAVE FNSAVE instruction This ...

Page 172: ...eal number Nmeans integer In most cases only the exponent is changed and the mantissa significand remains unchanged However when the value being scaled in ST 0 is a denormal value the mantissa is also changed and the result may turn out to be a normalized number Similarly if overflow or underflow results from a scale operation the resulting mantissa will differ from the source s mantissa The FSCAL...

Page 173: ...e operand is an SNaN value or unsupported format D Source operand is a denormal value U Result is too small for destination format O Result is too large for destination format P Value cannot be represented exactly in destination format Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Protected Mode Excepti...

Page 174: ...operand is outside the acceptable range the C2 flag in the FPU status word is set and the value in register ST 0 remains unchanged The instruction does not raise an exception when the source operand is out of range It is up to the program to check the C2 flag for out of range conditions Source values outside the range 263 to 263 can be reduced to the range of the instruction by subtracting an appr...

Page 175: ...ndefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Floating point Exceptions IS Stack underflow occurred IA Source operand is an SNaN value or unsupported format D Source operand is a denormal value P Value cannot be represented exactly in destination format Protected Mode Exceptions NM EM or TS in ...

Page 176: ...f the source operand is outside the acceptable range the C2 flag in the FPU status word is set and the value in register ST 0 remains unchanged The instruction does not raise an exception when the source operand is out of range It is up to the program to check the C2 flag for out of range conditions Source values outside the range 263 to 263 can be reduced to the range of the instruction by subtra...

Page 177: ... Undefined Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Floating point Exceptions IS Stack underflow occurred IA Source operand is an SNaN value or unsupported format D Source operand is a denormal value U Result is too small for destination format P Value cannot be represented exactly in destination f...

Page 178: ...IA exception Operation ST 0 SquareRoot ST 0 FPU Flags Affected C1 Set to 0 if stack underflow occurred Indicates rounding direction if inexact result exception P is generated 0 not roundup 1 roundup C0 C2 C3 Undefined Floating point Exceptions IS Stack underflow occurred IA Source operand is an SNaN value or unsupported format Source operand is a negative value except for 0 D Source operand is a d...

Page 179: ...anium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 180: ...nding mode specified by the RC field of the FPU control word and the exponent is converted to the width and bias of the destination format If the value being stored is too large for the destination format a numeric overflow exception O is generated and if the exception is unmasked no value is stored in the destination operand If the value being stored is a denormal value the denormal exception D i...

Page 181: ...ult Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS regi...

Page 182: ... GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 183: ...n Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a m...

Page 184: ...y operand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned me...

Page 185: ...nt instructions preceding the FSTENV FNSTENV instruction in the instruction stream have been executed These instructions are often used by exception handlers because they provide access to the FPU instruction and data pointers The environment is typically saved in the procedure stack Masking all exceptions after saving the environment prevents floating point exceptions from interrupting the except...

Page 186: ...is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outsi...

Page 187: ...r instructions The status stored in the AX register is thus guaranteed to be from the completion of the prior FPU instruction Operation DEST FPUStatusWord FPU Flags Affected The C0 C1 C2 and C3 are undefined Floating point Exceptions None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Itanium Mem FaultsVHPT Data Fault Nested TLB Fault...

Page 188: ...ault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions GP 0 If a memory operand...

Page 189: ...r this instruction is FSUB rather than FSUBP The FISUB instructions convert an integer source operand to extended real format before performing the subtraction The following table shows the results obtained when subtracting various classes of numbers from one another assuming that neither overflow nor underflow occurs Here the SRC value is subtracted from the DEST value DEST SRC result When the di...

Page 190: ...tes rounding direction if the inexact result exception P fault is generated 0 not roundup 1 roundup C0 C2 C3 Undefined Floating point Exceptions IS Stack underflow occurred IA Operand is an SNaN value or unsupported format Operands are infinities of like sign D Source operand is a denormal value U Result is too small for destination format O Result is too large for destination format P Value canno...

Page 191: ... memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES F...

Page 192: ...op the register stack the processor marks the ST 0 register as empty and increments the stack pointer TOP by 1 The no operand version of the floating point reverse subtract instructions always results in the register stack being popped In some assemblers the mnemonic for this instruction is FSUBR rather than FSUBRP The FISUBR instructions convert an integer source operand to extended real format b...

Page 193: ...ion is generated Notes Fmeans finite real number Imeans integer indicates floating point invalid arithmetic operand IA exception Operation IF instruction is FISUBR THEN DEST ConvertExtendedReal SRC DEST ELSE source operand is real number DEST SRC DEST FI IF instruction FSUBRP THEN PopRegisterStack FI FPU Flags Affected C1 Set to 0 if stack underflow occurred Indicates rounding direction if the ine...

Page 194: ...ault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit NM EM or TS in CR0 is set PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an ...

Page 195: ...eration CASE relation of operands OF Not comparable C3 C2 C0 111 ST 0 0 0 C3 C2 C0 000 ST 0 0 0 C3 C2 C0 001 ST 0 0 0 C3 C2 C0 100 ESAC FPU Flags Affected C1 Set to 0 if stack underflow occurred otherwise cleared to 0 C0 C2 C3 See above table Floating point Exceptions IS Stack underflow occurred IA One or both operands are NaN values or have unsupported formats D One or both operands are denormal ...

Page 196: ...Volume 4 Base IA 32 Instruction Reference 4 189 FTST TEST Continued Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 197: ...operands is a NaN value of any kind or is in an unsupported format As with the FCOM instructions if the operation results in an invalid arithmetic operand exception being raised the condition code flags are set only if the exception is masked The FUCOMP instructions pop the register stack following the comparison operation and the FUCOMPP instructions pops the register stack twice following the co...

Page 198: ...0 C2 C3 See table on previous page Floating point Exceptions IS Stack underflow occurred IA One or both operands are SNaN values or have unsupported formats Detection of a QNaN value in and of itself does not raise an invalid operand exception D One or both operands are denormal values Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Na...

Page 199: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...

Page 200: ... class of value or number in ST 0 OF Unsupported C3 C2 C0 000 NaN C3 C2 C0 001 Normal C3 C2 C0 010 Infinity C3 C2 C0 011 Zero C3 C2 C0 100 Empty C3 C2 C0 101 Denormal C3 C2 C0 110 ESAC FPU Flags Affected C1 Sign of value in ST 0 C0 C2 C3 See table above Floating point Exceptions None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT ...

Page 201: ...Base IA 32 Instruction Reference FXAM Examine Continued Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 202: ...s the square root of the third register from the top of the register stack FXCH ST 3 FSQRT FXCH ST 3 Operation IF number of operands is 1 THEN temp ST 0 ST 0 SRC SRC temp ELSE temp ST 0 ST 0 ST 1 ST 1 temp FI FPU Flags Affected C1 Set to 0 if stack underflow occurred otherwise cleared to 0 C0 C2 C3 Undefined Floating point Exceptions IS Stack underflow occurred Additional Itanium System Environmen...

Page 203: ...4 196 Volume 4 Base IA 32 Instruction Reference FXCH Exchange Register Contents Continued Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 204: ...ling operations The FXTRACT instruction is also useful for converting numbers in extended real format to decimal representations e g for printing or displaying If the floating point zero divide exception Z is masked and the source operand is zero an exponent value of is stored in register ST 1 and 0 with the sign of the source operand is stored in register ST 0 Operation TEMP Significand ST 0 ST 0...

Page 205: ...truction Reference FXTRACT Extract Exponent and Significand Continued Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode Exceptions NM EM or TS in CR0 is set Virtual 8086 Mode Exceptions NM EM or TS in CR0 is set ...

Page 206: ...s masked and register ST 0 contains 0 the instruction returns with a sign that is the opposite of the sign of the source operand in register ST 1 The FYL2X instruction is designed with a built in multiplication to optimize the calculation of logarithms with an arbitrary positive base b logbx log2b 1 log2x Operation ST 1 ST 1 log2ST 0 PopRegisterStack FPU Flags Affected C1 Set to 0 if stack underfl...

Page 207: ...rand is an SNaN or unsupported format Source operand in register ST 0 is a negative finite value not 0 Z Source operand in register ST 0 is 0 D Source operand is a denormal value U Result is too small for destination format O Result is too large for destination format P Value cannot be represented exactly in destination format Protected Mode Exceptions NM EM or TS in CR0 is set Real Address Mode E...

Page 208: ...ST 0 that are close to 0 When the epsilon value is small more significant digits can be retained by using the FYL2XP1 instruction than by using 1 as an argument to the FYL2X instruction The 1 expression is commonly found in compound interest and annuity calculations The result can be simply converted into a value in another logarithm base by including a scale factor in the ST 1 source operand The ...

Page 209: ...Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Floating point Exceptions IS Stack underflow occurred IA Either operand is an SNaN value or unsupported format D Source operand is a denormal value U Result is too small for destination format O Result is too large for destination format P Value cannot be represented exactly in destination format Protected Mode Exceptions NM...

Page 210: ...rivileged instruction When the processor is running in protected or virtual 8086 mode the privilege level of a program or procedure must to 0 to execute the HLT instruction Operation IF Itanium System Environment THEN IA 32_Intercept INST HALT Enter Halt state Flags Affected None Additional Itanium System Environment Exceptions IA 32_Intercept Mandatory Instruction Intercept Protected Mode Excepti...

Page 211: ...F OpernadSize 8 word byte operation THEN temp AX SRC signed division IF temp 7FH OR temp 80H if a positive result is greater than 7FH or a negative result is less than 80H THEN DE divide error ELSE AL temp AH AX SignedModulus SRC FI ELSE IF OpernadSize 16 doubleword word operation THEN Opcode Instruction Description F6 7 IDIV r m8 Signed divide AX where AH must contain sign extension of AL by r m ...

Page 212: ...ons Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions DE If the source operand divisor is 0 The signed result...

Page 213: ...limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions DE If the source operand divisor is 0 The signed result quotient is too large for the destination GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault...

Page 214: ...cond source operand an immediate value The product is then stored in the destination operand a general purpose register When an immediate value is used as an operand it is sign extended to the length of the destination operand format The CF and OF flags are set when significant bits are carried into the upper half of the result The CF and OF flags are cleared when the result fits exactly in the lo...

Page 215: ... the operands are signed or unsigned The CF and OF flags however cannot be used to determine if the upper half of the result is non zero Operation IF NumberOfOperands 1 THEN IF OperandSize 8 THEN AX AL SRC signed multiplication IF AH 00H OR AH FFH THEN CF 0 OF 0 ELSE CF 1 OF 1 FI ELSE IF OperandSize 16 THEN DX AX AX SRC signed multiplication IF DX 0000H OR DX FFFFH THEN CF 0 OF 0 ELSE CF 1 OF 1 FI...

Page 216: ...ault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code ...

Page 217: ...onment I O port references are mapped into the 64 bit virtual address pointed to by the IOBase register with four ports per 4K byte virtual page Operating systems can utilize the TLB in the Itanium architecture to grant or deny permission to any four I O ports The I O port space can be mapped into any arbitrary 64 bit physical memory location by operating system code If CFLG io is 1 and CPL IOPL t...

Page 218: ...LB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault IA_32_Exception Debug traps for data breakpoints and single step IA_32_Exception Alignment faults GP 0 Referenced Port is to an unimplemented virtual address or PSR dt is zero Protected Mode E...

Page 219: ...mission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the operand is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside t...

Page 220: ...e Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 221: ... The EDI register is incremented or decremented by 1 for byte operations by 2 for word operations or by 4 for doubleword operations The INS INSB INSW and INSD instructions can be preceded by the REP prefix for block input of ECX bytes words or doublewords This instruction is only useful for accessing I O ports located in the processor s I O address space I O transactions are performed after all pr...

Page 222: ...PL THEN Protected mode or virtual 8086 mode with CPL IOPL IF CFLG io AND Any I O Permission Bit for I O port being accessed 1 THEN GP 0 FI ELSE I O operation is allowed FI IF Itanium_System_Environment THEN SRC_VA IOBase Port 15 2 12 Port 11 0 SRC_PA translate SRC_VA DEST SRC_PA Reads from I O port FI memory_fence DEST SRC memory_fence IF byte transfer THEN IF DF 0 THEN E DI 1 ELSE E DI 1 FI ELSE ...

Page 223: ...is greater than has less privilege the I O privilege level IOPL and any of the corresponding I O permission bits in TSS for the I O port being accessed is 1 and when CFLG io is 1 If the destination is located in a nonwritable segment If an illegal memory operand effective address in the ES segments is given PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned...

Page 224: ...ing the INTO and INT3 instructions is similar to that of a far call made with the CALL instruction The primary difference is that with the INTn instruction the EFLAGS register is pushed onto the stack before the return address The return address is a far address consisting of the current values of the CS and EIP registers Returns from interrupt procedures are handled with the IRET instruction whic...

Page 225: ...ase linear address and limit of the IDT The initial base address value of the IDTR after the processor is powered up or reset is 0 Operation The following operational description applies not only to the INTn and INTO instructions but also to external interrupts and exceptions IF Itanium System EnvironmentTHEN IF INT3 Form THEN IA_32_Exception 3 IF INTO Form THEN IA_32_Exception 4 IF INT Form THEN ...

Page 226: ...ECTED MODE IF DEST 8 7 is not within IDT limits OR selected IDT descriptor is not an interrupt trap or task gate type THEN GP DEST 8 2 EXT EXT is bit 0 in error code FI IF software interrupt generated by INTn INT3 or INTO THEN IF gate descriptor DPL CPL THEN GP vector number 8 2 PE 1 DPL CPL software interrupt FI FI IF gate not present THEN NP vector number 8 2 EXT FI IF task gate specified in the...

Page 227: ...T FI Read trap or interrupt handler descriptor IF descriptor does not indicate a code segment OR code segment descriptor DPL CPL THEN GP selector EXT FI IF trap or interrupt gate segment is not present THEN NP selector EXT FI IF code segment is non conforming AND DPL CPL THEN IF VM 0 THEN GOTO INTER PRIVILEGE LEVEL INTERRUPT PE 1 interrupt or trap gate nonconforming code segment DPL CPL VM 0 ELSE ...

Page 228: ...elector s RPL DPL of code segment THEN TS SS selector EXT FI Read segment descriptor for stack segment in GDT or LDT IF stack segment DPL DPL of code segment OR stack segment does not indicate writable data segment THEN TS SS selector EXT FI IF stack segment not present THEN SS SS selector EXT FI IF 32 bit gate THEN IF new stack does not have room for 24 bytes error code pushed OR 20 bytes no erro...

Page 229: ...ackAddress 7 TSS limit THEN TS current TSS selector FI NewSS TSSstackAddress 4 NewESP stack address ELSE TSS is 16 bit TSSstackAddress new code segment DPL 4 2 IF TSSstackAddress 4 TSS limit THEN TS current TSS selector FI NewESP TSSstackAddress NewSS TSSstackAddress 2 FI IF segment selector is null THEN TS EXT FI IF segment selector index is not within its descriptor table limits OR segment selec...

Page 230: ...ERURPT_TO_PRIV0 FI ELSE Gate DPL 3 GP 0 FI ELSE IOPL 3 GP 0 FI ELSE VME 1 Check whether interrupt is directed for INT n instruction only executes virtual 8086 interupt protected mode interrupt or faults Ptr TSS 66 Fetch IO permission bitmpa pointer IF BIT Ptr 32 N 0 software redirection bitmap is 32 bytes below IO Permission THEN Interrupt redirected Goto VM86_INTERRUPT_TO_VM86 ELSE IF IOPL 3 THEN...

Page 231: ...d mode FS 0 DS 0 ES 0 CS Gate CS IF OperandSize 32 THEN EIP Gate instruction pointer ELSE OperandSize is 16 EIP Gate instruction pointer AND 0000FFFFH FI Starts execution of new routine in Protected Mode END VM86_INTERRUPT_TO_VM86 IF IOPL 3 THEN push FLAGS OR 3000H Push FLAGS w IOPL bits as 11B or IOPL 3 push CS push IP CS N 4 2 N is vector num read from interrupt table IP N 4 FLAGS FLAGS AND 7CD5...

Page 232: ...truction 3 words padded to 4 CS EIP Gate CS EIP segment descriptor information also loaded Push ErrorCode if any ELSE 16 bit gate Push FLAGS Push far pointer to return location 2 words CS IP Gate CS IP segment descriptor information also loaded Push ErrorCode if any FI CS RPL CPL IF interrupt gate THEN IF 0 FI TF 0 NT 0 VM 0 RF 0 FI END Flags Affected The EFLAGS register is pushed onto stack The I...

Page 233: ...of the stack segment and no stack switch occurs SS selector If the SS register is being loaded and the segment pointed to is marked not present If pushing the return address flags error code or stack segment pointer exceeds the bounds of the stack segment NP selector If code segment interrupt trap or task gate or TSS is not present TS selector If the RPL of the stack segment selector in the TSS is...

Page 234: ... not point to a segment descriptor for a code segment If the segment selector for a TSS has its local global bit set for local SS selector If the SS register is being loaded and the segment pointed to is marked not present If pushing the return address flags error code stack segment pointer or data segments exceeds the bounds of the stack segment NP selector If code segment interrupt trap or task ...

Page 235: ...implemented differently on future Intel architecture processors Use this instruction with care Data cached internally and not written back to main memory will be lost Unless there is a specific requirement or benefit to flushing caches without writing back modified cache lines for example testing or fault recovery where cache coherency with main memory is not a concern software should use the WBIN...

Page 236: ...e IA 32 Instruction Reference 4 229 INVD Invalidate Internal Caches Continued Intel Architecture Compatibility This instruction is not supported on Intel architecture processors earlier than the Intel486 processor ...

Page 237: ...he INVLPG instruction normally flushes the TLB entry only for the specified page however in some cases it flushes the entire TLB Operation IF Itanium System Environment THEN IA 32_Intercept INST INVLPG Flush RelevantTLBEntries Continue Continue execution Flags Affected None Additional Itanium System Environment Exceptions IA 32_Intercept Mandatory Instruction Intercept Protected Mode Exceptions GP...

Page 238: ...ng on the setting of these flags the processor performs the following types of interrupt returns Real Mode Return from virtual 8086 mode Return to virtual 8086 mode Intra privilege level return Inter privilege level return Return from nested task task switch All forms of IRET result in an IA 32_Intercept Inst IRET in the Itanium System Environment If the NT flag EFLAGS register is cleared the IRET...

Page 239: ...st IRET IF PE 0 THEN GOTO REAL ADDRESS MODE ELSE GOTO PROTECTED MODE FI REAL ADDRESS MODE IF OperandSize 32 THEN IF top 12 bytes of stack not within stack limits THEN SS FI IF instruction pointer not within code segment limits THEN GP 0 FI EIP Pop CS Pop 32 bit pop high order 16 bits discarded tempEFLAGS Pop EFLAGS tempEFLAGS AND 257FD5H OR EFLAGS AND 1A0000H ELSE OperandSize 16 IF top 6 bytes of ...

Page 240: ...RET is executed and stays in virtual 8086 mode IF CR4 VME 0 THEN IF IOPL 3 Virtual mode PE 1 VM 1 IOPL 3 THEN IF OperandSize 32 THEN IF top 12 bytes of stack not within stack limits THEN SS 0 FI IF instruction pointer not within code segment limits THEN GP 0 FI EIP Pop CS Pop 32 bit pop high order 16 bits discarded EFLAGS Pop VM IOPL VIP and VIF EFLAGS bits are not modified by pop ELSE OperandSize...

Page 241: ...GP 0 ELSE IP Pop Word Pops CS Pop 0 TempFlags Pop FLAGS IOPL IF and TF are not modified FLAGS FLAGS AND 3302H OR TempFlags AND 4CD5H EFLAGS VIF TempFlags IF FI ELSE OperandSize 32 GP 0 FI FI END RETURN TO VIRTUAL 8086 MODE Interrupted procedure was in virtual 8086 mode PE 1 VM 1 in flags image IF top 24 bytes of stack are not within stack segment limits THEN SS 0 FI IF instruction pointer not with...

Page 242: ...0 FI IF return code segment selector addrsses descriptor beyond descriptor table limit THEN GP selector FI Read segment descriptor pointed to by the return code segment selector IF return code segment descriptor is not a code segment THEN GP selector FI IF return code segment selector RPL CPL THEN GP selector FI IF return code segment descriptor is conforming AND return code segment DPL return cod...

Page 243: ...F stack segment selector RPL RPL of the return code segment selector IF stack segment selector RPL RPL of the return code segment selector OR the stack segment descriptor does not indicate a a writable data segment OR stack segment DPL RPL of the return code segment selector THEN GP SS selector FI IF stack segment is not present THEN NP SS selector FI IF tempEIP is not within code segment limit TH...

Page 244: ...n pointer is not within the return code segment limit GP selector If a segment selector index is outside its descriptor table limits If the return code segment selector RPL is greater than the CPL If the DPL of a conforming code segment is greater than the return code segment selector RPL If the DPL for a nonconforming code segment is not equal to the RPL of the code segment selector If the stack ...

Page 245: ...e segment limit SS If the top bytes of stack are not within stack limits Virtual 8086 Mode Exceptions GP 0 If the return instruction pointer is not within the return code segment limit IF IOPL not equal to 3 PF fault code If a page fault occurs SS 0 If the top bytes of stack are not within stack limits AC 0 If an unaligned memory reference occurs and alignment checking is enabled ...

Page 246: ...y CF 0 75 cb JNE rel8 Jump short if not equal ZF 0 7E cb JNG rel8 Jump short if not greater ZF 1 or SF OF 7C cb JNGE rel8 Jump short if not greater or equal SF OF 7D cb JNL rel8 Jump short if not less SF OF 7F cb JNLE rel8 Jump short if not less or equal ZF 0 and SF OF 71 cb JNO rel8 Jump short if not overflow OF 0 7B cb JNP rel8 Jump short if not parity PF 0 79 cb JNS rel8 Jump short if not sign ...

Page 247: ...less and greater are used for comparisons of signed integers and the terms above and below are used for unsigned integers Opcode Instruction Description 0F 8D cw cd JGE rel16 32 Jump near if greater or equal SF OF 0F 8C cw cd JL rel16 32 Jump near if less SF OF 0F 8E cw cd JLE rel16 32 Jump near if less or equal ZF 1 or SF OF 0F 86 cw cd JNA rel16 32 Jump near if not above CF 1 or ZF 1 0F 82 cw cd...

Page 248: ...FARLABEL BEYOND The JECXZ and JCXZ instructions differs from the other Jcc instructions because they do not check the status flags Instead they check the contents of the ECX and CX registers respectively for 0 These instructions are useful at the beginning of a conditional loop that terminates with a conditional loop instruction such as LOOPNE They prevent entering the loop when the ECX or CX regi...

Page 249: ...the CS segment or is outside of the effective address space from 0 to FFFFH This condition can occur if 32 address size override prefix is used Virtual 8086 Mode Exceptions GP 0 If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH This condition can occur if 32 address size override prefix is used ...

Page 250: ...set from the base of the code segment or a relative offset a signed offset relative to the current value of the instruction pointer in the EIP register An absolute address is specified directly in a register or indirectly in a memory location r m16 or r m32 operand form A relative offset rel8 rel16 or rel32 is generally specified as a label in assembly code but at the machine code level it is enco...

Page 251: ...he previous paragraph except that the processor checks the access rights of the code segment being jumped to An far jump through a call gate A task switch Results in an IA 32_Intercept Gate in Itanium System Environment The JMP instruction cannot be used to perform inter privilege level jumps When executing an far jump through a call gate the segment selector specified by the target operand identi...

Page 252: ...32 or m16 32 IF OperandSize 32 THEN EIP tempEIP DEST is ptr16 32 or m16 32 ELSE OperandSize 16 EIP tempEIP AND 0000FFFFH clear upper 16 bits FI IF Itanium System Environment AND PSR tb THEN IA_32_Exception Debug FI IF far call AND PE 1 AND VM 0 Protected mode not virtual 8086 mode THEN IF effective address in the CS DS ES FS GS or SS segment is illegal OR segment selector in target operand null TH...

Page 253: ...P tempEIP IF Itanium System Environment AND PSR tb THEN IA_32_Exception Debug END CALL GATE IF call gate DPL CPL OR call gate DPL call gate segment selector RPL THEN GP call gate selector FI IF call gate not present THEN NP call gate selector FI IF Itanium System Environment THEN IA 32_Intercept Gate JMP IF call gate code segment selector is null THEN GP 0 FI IF call gate code segment selector ind...

Page 254: ...selector FI IF Itanium System Environment THENIA 32_Intercept Gate JMP SWITCH TASKS to TSS IF EIP not within code segment limit THEN GP 0 FI END Flags Affected All flags are affected if a task switch occurs no flags are affected if a task switch does not occur Additional Itanium System Environment Exceptions Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault...

Page 255: ...he segment selector for a TSS has its local global bit set for local If a TSS segment descriptor specifies that the TSS is busy or not available SS 0 If a memory operand effective address is outside the SS segment limit NP selector If the code segment being accessed is not present If call gate task gate or TSS not present PF fault code If a page fault occurs AC 0 If alignment checking is enabled a...

Page 256: ...4 bit virtual address space within virtual region 0 GR 1 is loaded with the next sequential instruction address following JMPE If PSR di is 1 the instruction is nullified and a Disabled Instruction Set Transition fault is generated If Itanium branch debugging is enabled an IA_32_Exception Debug trap is taken after JMPE completes execution JMPE can be performed at any privilege level and does not c...

Page 257: ...3 32 0 zero extend from 32 bits to 64 bits GR 1 31 0 EIP AR CSD base next sequential instruction address GR 1 63 32 0 PSR id EFLAG rf 0 IF PSR tb taken branch trap IA_32_Exception Debug Flags Affected None other than EFLAG rf Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Fault Disabled ISA Disabled Instruction Set Transition Fault if PSR di is 1 IA_32...

Page 258: ...nd 5 of the EFLAGS register are set in the AH register as shown in the Operation below Operation AH EFLAGS SF ZF 0 AF 0 PF 1 CF Flags Affected None that is the state of the flags in the EFLAGS register are not affected Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Exceptions All Operating Modes None Opcode Instruction Description 9F LAHF Load AH...

Page 259: ...pe and DPL fields Here the two lower order bytes of the doubleword are masked by FF00H before being loaded into the destination operand This instruction performs the following checks before it loads the access rights in the destination register Checks that the segment selector is not null Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being acce...

Page 260: ...tem Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Table 2 15 LAR Descriptor Validity Type Name Valid 0 Reser...

Page 261: ...ull segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Only occurs when fetching target from memory Real Address Mode Exceptions UD The LAR instruction is not recognized in real address mode Virtual 8086...

Page 262: ... ES FS or GS registers without causing a protection exception Any subsequent reference to a segment whose corresponding segment register is loaded with a null selector causes a general protection exception GP and no memory reference to the segment occurs Operation IF ProtectedMode THEN IF SS is loaded THEN IF SegementSelector null THEN GP 0 FI ELSE IF Segment selector index is not within descripto...

Page 263: ...tor SRC FI DEST Offset SRC Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty...

Page 264: ...being loaded with a non null segment selector and the segment is marked not present PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is...

Page 265: ...RC 16 bit address ELSE IF OperandSize 16 AND AddressSize 32 THEN temp EffectiveAddress SRC 32 bit address DEST temp 0 15 16 bit address ELSE IF OperandSize 32 AND AddressSize 16 THEN temp EffectiveAddress SRC 16 bit address DEST ZeroExtend temp 32 bit address ELSE IF OperandSize 32 AND AddressSize 32 THEN DEST EffectiveAddress SRC 32 bit address FI FI Opcode Instruction Description 8D r LEA r16 m ...

Page 266: ...nal Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Protected Mode Exceptions UD If source operand is not a memory location Real Address Mode Exceptions UD If source operand is not a memory location Virtual 8086 Mode Exceptions UD If source operand is not a memory location ...

Page 267: ...e calling procedure and remove any arguments pushed onto the stack by the procedure being returned from Operation IF StackAddressSize 32 THEN ESP EBP ELSE StackAddressSize 16 SP BP FI IF OperandSize 32 THEN EBP Pop ELSE OperandSize 16 BP Pop FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Ne...

Page 268: ... Exit Continued Real Address Mode Exceptions GP If the EBP register points to a location outside of the effective address space from 0 to 0FFFFH Virtual 8086 Mode Exceptions GP 0 If the EBP register points to a location outside of the effective address space from 0 to 0FFFFH ...

Page 269: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...

Page 270: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...

Page 271: ...operand is not used and the high order byte of the base address in the GDTR or IDTR is filled with zeros The LGDT and LIDT instructions are used only in operating system software they are not used in application programs They are the only instructions that directly load a linear address that is not a segment relative address and a limit in protected mode They are commonly executed in real address ...

Page 272: ...ccess memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs Real Address Mode Exceptions UD If source operand is not a memory location GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit...

Page 273: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...

Page 274: ...he LAR VERR VERW or LSL instructions cause a general protection exception GP The operand size attribute has no effect on this instruction The LLDT instruction is provided for use in operating system software it should not be used in application programs Also this instruction can only be executed in protected mode Operation IF Itanium System Environment THEN IA 32_Intercept INST LLDT IF SRC Offset ...

Page 275: ...T is not a Local Descriptor Table Segment selector is beyond GDT limit SS 0 If a memory operand effective address is outside the SS segment limit NP selector If the LDT descriptor is not present PF fault code If a page fault occurs Real Address Mode Exceptions UD The LLDT instruction is not recognized in real address mode Virtual 8086 Mode Exceptions UD The LLDT instruction is recognized in virtua...

Page 276: ...Volume 4 Base IA 32 Instruction Reference 4 269 LIDT Load Interrupt Descriptor Table Register See entry for LGDT LIDT Load Global Descriptor Table Register Load Interrupt Descriptor Table Register ...

Page 277: ...ot be used in application programs In protected or virtual 8086 mode it can only be executed at CPL 0 This instruction is provided for compatibility with the Intel 286 processor programs and procedures intended to run on processors more recent than the Intel 286 should use the MOV control registers instruction to load the machine status word This instruction is a serializing instruction Operation ...

Page 278: ...nd effective address is outside the CS DS ES FS or GS segment limit Virtual 8086 Mode Exceptions GP 0 If the current privilege level is not 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs ...

Page 279: ...d by the alignment of the memory field Memory locking is observed for arbitrarily misaligned fields Operation IF Itanium System Environment AND External_Bus_Lock_Required AND DCR lc THEN IA 32_Intercept LOCK AssertLOCK DurationOfAccompaningInstruction Flags Affected None Additional Itanium System Environment Exceptions Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Dat...

Page 280: ...ruction not listed in the Description section above Other exceptions can be generated by the instruction that the LOCK prefix is being applied to Virtual 8086 Mode Exceptions UD If the LOCK prefix is used with an instruction not listed in the Description section above Other exceptions can be generated by the instruction that the LOCK prefix is being applied to ...

Page 281: ...ister is decremented The ESI register is incremented or decremented by 1 for byte operations by 2 for word operations or by 4 for doubleword operations The LODS LODSB LODSW and LODSD instructions can be preceded by the REP prefix for block loads of ECX bytes words or doublewords More often however these instructions are used within a LOOP construct because further processing of the data moved into...

Page 282: ...ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outsid...

Page 283: ...the instruction pointer Offsets of 128 to 127 are allowed with this instruction Some forms of the loop instruction LOOPcc also accept the ZF flag as a condition for terminating the loop before the count reaches zero With these forms of the instruction a condition code cc is associated with each instruction to indicate the condition being tested for Here the LOOPcc instruction itself does not affec...

Page 284: ...d DEST IF OperandSize 16 THEN EIP EIP AND 0000FFFFH FI IF Itanium System Environment AND PSR tb THEN IA_32_Exception Debug ELSE Terminate loop and continue program execution at EIP FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort IA_32_Exception Taken Branch Debug Exception if PSR tb is 1 Protected Mode Exceptions GP 0 If the...

Page 285: ...t raw limit left 12 bits and filling the low order 12 bits with 1s When the operand size is 32 bits the 32 bit byte limit is stored in the destination operand When the operand size is 16 bits a valid 32 bit limit is computed however the upper 16 bits are truncated and only the low order 16 bits are loaded into the destination operand This instruction performs the following checks before it loads t...

Page 286: ...OR 00000FFFH FI IF OperandSize 32 THEN DEST temp ELSE OperandSize 16 DEST temp AND FFFFH FI FI Flags Affected The ZF flag is set to 1 if the segment limit is loaded successfully otherwise it is cleared to 0 Type Name Valid 0 Reserved No 1 Available 16 bit TSS Yes 2 LDT Yes 3 Busy 16 bit TSS Yes 4 16 bit call gate No 5 16 bit 32 bit task gate No 6 16 bit trap gate No 7 16 bit interrupt gate No 8 Re...

Page 287: ... Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory ref...

Page 288: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...

Page 289: ...n initialization code to establish the first task to be executed The operand size attribute has no effect on this instruction Operation IF Itanium System Environment THEN IA 32_Intercept INST LTR IF SRC Offset descriptor table limit OR IF SRC type global THEN GP segment selector FI Reat segment descriptor IF segment descriptor is not for an available TSS THEN GP segment selector FI IF segment desc...

Page 290: ... If the selector points to LDT or is beyond the GDT limit NP selector If the TSS is marked not present SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs Real Address Mode Exceptions UD The LTR instruction is not recognized in real address mode Virtual 8086 Mode Exceptions UD The LTR instruction is not recognized in virtual 8086 mode ...

Page 291: ...The MOV instruction cannot be used to load the CS register Attempting to do so results in an invalid opcode exception UD To load the CS register use the RET instruction Opcode Instruction Description 88 r MOV r m8 r8 Move r8 to r m8 89 r MOV r m16 r16 Move r16 to r m16 89 r MOV r m32 r32 Move r32 to r m32 8A r MOV r8 r m8 Move r m8 to r8 8B r MOV r16 r m16 Move r m16 to r16 8B r MOV r32 r m32 Move...

Page 292: ...System Environment MOV to SS results in a IA 32_Intercept SystemFlag trap after the instruction completes This operation allows a stack pointer to be loaded into the ESP register with the next instruction MOV ESP stack pointer value before an interrupt occurs The LSS instruction offers a more efficient method of loading the SS and ESP registers When moving data in 32 bit mode between a segment reg...

Page 293: ...ister Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If attempt is made to load SS register with null segment selector If the destina...

Page 294: ... alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 UD If attempt is made to load the CS register Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit UD If attempt is made to load the CS register Virtua...

Page 295: ...in the control registers PE and PG in register CR0 and PGE PSE and PAE in register CR4 all TLB entries are flushed including global entries This operation is implementation specific for the Pentium Pro processor Software should not depend on this functionality in future Intel architecture processors If the PG flag is set to 1 and control register CR4 is written to set the PAE flag to 1 to enable t...

Page 296: ... Protected Mode Exceptions GP 0 If the current privilege level is not 0 If an attempt is made to write a 1 to any reserved bit in CR4 If an attempt is made to write reserved bits in the page directory pointers table used in the extended physical addressing mode when the PAE flag in control register CR4 and the PG flag in control register CR0 are set to 1 Real Address Mode Exceptions GP If an attem...

Page 297: ...in an undefined opcode UD exception At the opcode level the reg field within the ModR M byte specifies which of the debug registers is loaded or read The two bits in the mod field are always 11 The r m field specifies the general purpose register loaded or read Operation IF Itanium System Environment THEN IA 32_Intercept INST MOVDR IF DE 1 and SRC or DEST DR4 or DR5 THEN UD ELSE DEST SRC Flags Aff...

Page 298: ...n debug register DR7 is set Real Address Mode Exceptions UD If the DE debug extensions bit of CR4 is set and a MOV instruction is executed involving DR4 or DR5 DB If any debug register is accessed while the GD flag in debug register DR7 is set Virtual 8086 Mode Exceptions GP 0 The debug registers cannot be loaded or read when in virtual 8086 mode ...

Page 299: ...ters are incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register If the DF flag is 0 the ESI and EDI register are incremented if the DF flag is 1 the ESI and EDI registers are decremented The registers are incremented or decremented by 1 for byte operations by 2 for word operations or by 4 for doubleword operations The MOVS MOVSB MOVSW and MOVSD inst...

Page 300: ...rand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If ...

Page 301: ...address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operan...

Page 302: ...ot Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the...

Page 303: ...6 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 304: ...otherwise the flags are set Operation IF byte operation THEN AX AL SRC ELSE word or doubleword operation IF OperandSize 16 THEN DX AX AX SRC ELSE OperandSize 32 EDX EAX EAX SRC FI FI Flags Affected The OF and CF flags are cleared to 0 if the upper half of the result is 0 otherwise they are set to 1 The SF ZF AF and PF flags are undefined Additional Itanium System Environment Exceptions Itanium Reg...

Page 305: ...nment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or G...

Page 306: ...iss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS ...

Page 307: ...86 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 308: ...yte instruction that takes up space in the instruction stream but does not affect the machine context except the EIP register The NOP instruction performs no operation no registers are accessed and no faults are generated Flags Affected None Exceptions All Operating Modes None Opcode Instruction Description 90 NOP No operation ...

Page 309: ...ata Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination operand points to a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If...

Page 310: ...86 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 311: ...Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Opcode Instruction Description 0C ib OR AL imm8 AL OR imm8 0D iw OR AX imm16 AX OR imm16 0D i...

Page 312: ... occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside ...

Page 313: ...mapped into the 64 bit virtual address pointed to by the IOBase register with four ports per 4K byte virtual page Operating systems can utilize TLBs in the Itanium architecture to grant or deny permission to any four I O ports The I O port space can be mapped into any arbitrary 64 bit physical memory location by operating system code If CFLG io is 1 and CPL IOPL the TSS is consulted for I O permis...

Page 314: ...Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault IA_32_Exception Debug traps for data breakpoints and single step IA_32_Exception Alignment faults GP 0 Referenced Port is to an unimplemented virtual address or PSR dt is zero Protected Mode Exceptions...

Page 315: ...r is incremented if the DF flag is 1 the EDI register is decremented The ESI register is incremented or decremented by 1 for byte operations by 2 for word operations or by 4 for doubleword operations The OUTS OUTSB OUTSW and OUTSD instructions can be preceded by the REP prefix for block input of ECX bytes words or doublewords See REP REPE REPZ REPNE REPNZ Repeat String Operation Prefix on page 4 3...

Page 316: ...ermission bitmap the bitmap is not referenced If the referenced I O port is mapped to an unimplemented virtual address via the I O Base register or if data translations are disabled PSR dt is 0 a GPFault is generated on the referencing OUTS instruction Operation IF PE 1 AND VM 1 OR CPL IOPL THEN Protected mode or virtual 8086 mode with CPL IOPL IF CFLG io AND Any I O Permission Bit for I O port be...

Page 317: ...vel IOPL and any of the corresponding I O permission bits in TSS for the I O port being accessed is 1 and when CFLG io is 1 If the destination is located in a nonwritable segment If a memory operand effective address is outside the limit of the ES segment If the ES register contains a null segment selector If an illegal memory operand effective address in the ES segments is given PF fault code If ...

Page 318: ...S FS or GS register without causing a general protection fault However any subsequent attempt to reference a segment whose corresponding segment register is loaded with a null value causes a general protection exception GP In this situation no memory reference occurs and the saved value of the segment register is null The POP instruction cannot pop a value into the CS register To load the CS regis...

Page 319: ...estination Operation IF StackAddrSize 32 THEN IF OperandSize 32 THEN DEST SS ESP copy a doubleword ESP ESP 4 ELSE OperandSize 16 DEST SS ESP copy a word ESP ESP 2 FI ELSE StackAddrSize 16 IF OperandSize 16 THEN DEST SS SP copy a word SP SP 2 ELSE OperandSize 32 DEST SS SP copy a doubleword SP SP 4 FI FI Loading a segment register while in protected mode results in special checks and actions as des...

Page 320: ...S Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If attempt is made to load SS register with null seg...

Page 321: ... SS selector If the SS register is being loaded and the segment pointed to is marked not present NP If the DS ES FS or GS register is being loaded and the segment pointed to is marked not present PF fault code If a page fault occurs AC 0 If an unaligned memory reference is made while the current privilege level is 3 and alignment checking is enabled Real Address Mode Exceptions GP If a memory oper...

Page 322: ...e the same opcode The POPA instruction is intended for use when the operand size attribute is 16 and the POPAD instruction for when the operand size attribute is 32 Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used Others may treat these mnemonics as synonyms POPA POPAD and use the current setting of the operand size attribute to determine the size of ...

Page 323: ...ghts Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions SS 0 If the starting or ending stack address is not within the stack segment PF fault code If a page fault occurs Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mod...

Page 324: ...or in real address mode which is equivalent to privilege level 0 all the non reserved flags in the EFLAGS register except the VIP and VIF flags can be modified The VIP and VIF flags are cleared When operating in protected mode but with a privilege level greater an 0 all the flags can be modified except the IOPL field and the VIP and VIF flags Here the IOPL flags are masked and the VIP and VIF flag...

Page 325: ...d VIF can be modified IOPL is masked ELSE OperandSize 16 EFLAGS 15 0 Pop All non reserved bits except IOPL can be modified IOPL is masked FI FI ELSE In Virtual 8086 Mode IF IOPL 3 THEN IF OperandSize 32 THEN EFLAGS Pop All non reserved bits except VM RF IOPL VIP and VIF can be modified VM RF IOPL VIP and VIF are masked ELSE EFLAGS 15 0 Pop All non reserved bits except IOPL can be modified IOPL is ...

Page 326: ...Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault IA 32_Intercept System Flag Intercept Trap if CFLG ii is 1 and the IF flag changes state or if the AC RF or TF changes state Protected Mode Exceptions SS 0 If the top of stack is not within the stack segment Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS ...

Page 327: ...pushes the value of the ESP register as it existed before the instruction was executed Thus if a PUSH instruction uses a memory operand in which the ESP register is used as a base register for computing the operand address the effective address of the operand is computed before the ESP register is decremented In the real address mode if the ESP or SP register is 1 when the PUSH instruction is exec...

Page 328: ...Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the c...

Page 329: ...d and an unaligned memory reference is made Intel Architecture Compatibility For Intel architecture processors from the Intel 286 on the PUSH ESP instruction pushes the value of the ESP register as it existed before the instruction was executed This is also true in the real address and virtual 8086 modes For the Intel 8086 processor the PUSH SP instruction pushes the new value of the SP register t...

Page 330: ... is 16 and the PUSHAD instruction for when the operand size attribute is 32 Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when PUSHAD is used Others may treat these mnemonics as synonyms PUSHA PUSHAD and use the current setting of the operand size attribute to determine the size of values to be pushed from the stack regardless of the mnemonic used In the real addres...

Page 331: ...ta Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions SS 0 If the starting or ending stack address is outside the stack segment limit PF fault code If a page fault occurs Real Address Mode Exceptions GP If the ESP or SP register contains 7 9 11 13 or 15 Vi...

Page 332: ...e mnemonics as synonyms PUSHF PUSHFD and use the current setting of the operand size attribute to determine the size of values to be pushed from the stack regardless of the mnemonic used When the I O privilege level IOPL is less than 3 in virtual 8086 mode the PUSHF PUSHFD instructions causes a general protection exception GP The IOPL is altered only when executing at privilege level 0 The interru...

Page 333: ...pFlags FI FI FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault ...

Page 334: ...times D1 3 RCR r m32 1 Rotate 33 bits CF r m32 right once D3 3 RCR r m32 CL Rotate 33 bits CF r m32 right CL times C1 3 ib RCR r m32 imm8 Rotate 33 bits CF r m32 right imm8 times D0 0 ROL r m8 1 Rotate 8 bits r m8 left once D2 0 ROL r m8 CL Rotate 8 bits r m8 left CL times C0 0 ib ROL r m8 imm8 Rotate 8 bits r m8 left imm8 times D1 0 ROL r m16 1 Rotate 16 bits r m16 left once D3 0 ROL r m16 CL Rot...

Page 335: ...The RCL and RCR instructions include the CF flag in the rotation The RCL instruction shifts the CF flag into the least significant bit and shifts the most significant bit into the CF flag The RCR instruction shifts the CF flag into the most significant bit and shifts the least significant bit into the CF flag For the ROL and ROR instructions the original value of the CF flag is not a part of the r...

Page 336: ...pCOUNT 1 OD IF COUNT 1 IF COUNT 1 THEN OF MSB DEST XOR MSB 1 DEST ELSE OF is undefined FI Flags Affected The CF flag contains the value of the bit shifted into it The OF flag is affected only for single bit rotates see Description above it is undefined for multi bit rotates The SF ZF AF and PF flags are not affected Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register C...

Page 337: ...e current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS...

Page 338: ...eption The MSRs control functions for testability execution tracing performance monitoring and machine check errors The CPUID instruction should be used to determine whether MSRs are supported EDX 5 1 before using this instruction See model specific instructions for all the MSRs that can be written to with this instruction and their addresses Operation IF Itanium System Environment THEN IA 32_Inte...

Page 339: ...on is not recognized in virtual 8086 mode Intel Architecture Compatibility The MSRs and the ability to read them with the RDMSR instruction were introduced into the Intel architecture with the Pentium processor Execution of this instruction by an Intel architecture processor earlier than the Pentium processor results in an invalid opcode exception UD ...

Page 340: ...oded number of interrupts received or number of cache loads The RDPMC instruction does not serialize instruction execution That is it does not imply that all the events caused by the preceding instructions have been completed or that events caused by subsequent instructions have not begun If an exact event count is desired software must use a serializing instruction such as the CPUID instruction b...

Page 341: ...rent privilege level is not 0 and the PCE flag in the CR4 register is clear In IA 32 System Environment If the value in the ECX register does not match an implemented performance counter Real Address Mode Exceptions GP If the PCE flag in the CR4 register is clear In the IA 32 System Environment If the value in the ECX register does not match an implemented performance counter Virtual 8086 Mode Exc...

Page 342: ...he Itanium System Environment PSR si and CR4 TSD restricts the use of the RDTSC instruction When PSR si is clear and CR4 TSD is clear the RDTSC instruction can be executed at any privilege level when PSR si is set or CR4 TSD is set the instruction can only be executed at privilege level 0 The RDTSC instruction is not serializing instruction Thus it does not necessarily wait until all previous inst...

Page 343: ... 1 or CR4 TSD is 1 and the CPL is greater than 0 Protected Mode Exceptions GP 0 If the TSD flag in register CR4 is set and the CPL is greater than 0 For the IA 32 System Environment only Real Address Mode Exceptions GP If the TSD flag in register CR4 is set For the IA 32 System Environment only Virtual 8086 Mode Exceptions GP 0 If the TSD flag in register CR4 is set For the IA 32 System Environmen...

Page 344: ...rom DS ESI to ES EDI F3 A5 REP MOVS m16 m16 Move ECX words from DS ESI to ES EDI F3 A5 REP MOVS m32 m32 Move ECX doublewords from DS ESI to ES EDI F3 6E REP OUTS DX r m8 Output ECX bytes from DS ESI to port DX F3 6F REP OUTS DX r m16 Output ECX words from DS ESI to port DX F3 6F REP OUTS DX r m32 Output ECX doublewords from DS ESI to port DX F3 AC REP LODS AL Load ECX bytes from DS ESI to AL F3 AD...

Page 345: ...rom the exception or interrupt handler The source and destination registers point to the next string elements to be operated on the EIP register points to the string instruction and the ECX register has the value it held following the last successful iteration of the instruction This mechanism allows long string operations to proceed without affecting the interrupt response time of the system When...

Page 346: ...t the status flags in the EFLAGS register Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit ...

Page 347: ...ting a near return the processor pops the return instruction pointer offset from the top of the procedure stack into the EIP register and begins program execution at the new instruction pointer The CS register is unchanged When executing a far return the processor pops the return instruction pointer from the top of the procedure stack into the EIP register then pops the segment selector from the t...

Page 348: ...anium System Environment AND PSR tb THEN IA_32_Exception Debug FI Real address mode or virtual 8086 mode IF PE 0 OR PE 1 AND VM 1 AND instruction far return THEN IF OperandSize 32 THEN IF top 12 bytes of stack not within stack limits THEN SS 0 FI EIP Pop CS Pop 32 bit pop high order 16 bits discarded ELSE OperandSize 16 IF top 6 bytes of stack not within stack limits THEN SS 0 FI tempEIP Pop tempE...

Page 349: ...N OUTER PRIVILEGE LEVEL ELSE GOTO RETURN TO SAME PRIVILEGE LEVEL FI END FI RETURN SAME PRIVILEGE LEVEL IF the return instruction pointer is not within ther return code segment limit THEN GP 0 FI IF OperandSize 32 THEN EIP Pop CS Pop 32 bit pop high order 16 bits discarded ESP ESP SRC ELSE OperandSize 16 EIP Pop EIP EIP AND 0000FFFFH CS Pop 16 bit pop ESP ESP SRC FI IF Itanium System Environment AN...

Page 350: ... pop segment descriptor information also loaded CS RPL CPL ESP ESP SRC tempESP Pop tempSS Pop 16 bit pop segment descriptor information also loaded segment descriptor information also loaded ESP tempESP SS tempSS FI FOR each of segment register ES FS GS and DS DO IF segment register points to data or non conforming code segment AND CPL segment descriptor DPL DPL in hidden part of segment register ...

Page 351: ...e RPL of the code segment s segment selector If the return code segment is conforming and the segment selector s DPL greater than the RPL of the code segment s segment selector If the stack segment is not a writable data segment If the stack segment selector RPL is not equal to the RPL of the return code segment selector If the stack segment descriptor DPL is not equal to the RPL of the return cod...

Page 352: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...

Page 353: ... a 32 KByte aligned address The contents of the model specific registers are not affected by a return from SMM See Chapter 9 in the Intel Architecture Software Developer s Manual Volume 3 for more information about SMM and the behavior of the RSM instruction Operation IF Itanium System Environment THEN IA 32_Intercept INST RSM ReturnFromSSM ProcessorState Restore SSMDump Flags Affected All Additio...

Page 354: ... 3 and 5 in the EFLAGS registers are set as shown in the Operation below Operation EFLAGS SF ZF 0 AF 0 PF 1 CF AH Flags Affected The SF ZF AF PF and CF flags are loaded with values from the AH register Bits 1 3 and 5 of the EFLAGS register are set to 1 0 and 0 respectively Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Exceptions All Operating Mo...

Page 355: ...d divide r m16 by 2 imm8 times D1 7 SAR r m32 1 Signed divide r m32 by 2 once D3 7 SAR r m32 CL Signed divide r m32 by 2 CL times C1 7 ib SAR r m32 imm8 Signed divide r m32 by 2 imm8 times D0 4 SHL r m8 1 Multiply r m8 by 2 once D2 4 SHL r m8 CL Multiply r m8 by 2 CL times C0 4 ib SHL r m8 imm8 Multiply r m8 by 2 imm8 times D1 4 SHL r m16 1 Multiply r m16 by 2 once D3 4 SHL r m16 CL Multiply r m16...

Page 356: ...ion clears the most significant bit the SAR instruction sets or clears the most significant bit to correspond to the sign most significant bit of the original value in the destination operand In effect the SAR instruction fills the empty bit position s shifted value with the sign of the unshifted value The SAR and SHR instructions can be used to perform signed or unsigned division respectively of ...

Page 357: ...ow for the various instructions IF COUNT 1 THEN IF instruction is SAL or SHL THEN OF MSB DEST XOR CF ELSE IF instruction is SAR THEN OF 0 ELSE instruction is SHR OF MSB tempDEST FI FI ELSE OF undefined FI Flags Affected The CF flag contains the value of the last bit shifted out of the destination operand it is undefined for SHL and SHR instructions count is greater than or equal to the size of the...

Page 358: ...mory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segme...

Page 359: ... of a multibyte or multiword subtraction in which a SUB instruction is followed by a SBB instruction Operation DEST DEST SRC CF Flags Affected The OF SF ZF AF PF and CF flags are set according to the result Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Opcode Instruction Description 1C ib SBB AL imm8 Subtract with borrow imm8 from AL 1D iw SBB A...

Page 360: ...ontains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory opera...

Page 361: ...F flag is 1 the EDI register is decremented The EDI register is incremented or decremented by 1 for byte operations by 2 for word operations or by 4 for doubleword operations The SCAS SCASB SCASW and SCASD instructions can be preceded by the REP prefix for block comparisons of ECX bytes words or doublewords More often however these instructions will be used in a LOOP construct that takes some acti...

Page 362: ...ult Protected Mode Exceptions GP 0 If a memory operand effective address is outside the limit of the ES segment If the ES register contains a null segment selector If an illegal memory operand effective address in the ES segment is given PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real A...

Page 363: ...r m8 Set byte if greater ZF 0 and SF OF 0F 9D SETGE r m8 Set byte if greater or equal SF OF 0F 9C SETL r m8 Set byte if less SF OF 0F 9E SETLE r m8 Set byte if less or equal ZF 1 or SF OF 0F 96 SETNA r m8 Set byte if not above CF 1 or ZF 1 0F 92 SETNAE r m8 Set byte if not above or equal CF 1 0F 93 SETNB r m8 Set byte if not below CF 0 0F 97 SETNBE r m8 Set byte if not below or equal CF 0 and ZF 0...

Page 364: ...nt Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination is located in a nonwr...

Page 365: ...6 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 366: ...ith 0s The SGDT and SIDT instructions are useful only in operating system software however they can be used in application programs Operation IF Itanium System Environment THEN IA 32_Intercept INST SGDT SIDT IF instruction is IDTR THEN IF OperandSize 16 THEN DEST 0 15 IDTR Limit DEST 16 39 IDTR Base 24 bits of base address loaded DEST 40 47 0 ELSE 32 bit Operand Size DEST 0 15 IDTR Limit DEST 16 4...

Page 367: ...ress Mode Exceptions UD If the destination operand is a register GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions UD If the destination operand is a register GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a m...

Page 368: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...

Page 369: ...t of the destination operand For a 1 bit shift the OF flag is set if a sign change occurred otherwise it is cleared If the count operand is 0 the flags are not affected The SHLD instruction is useful for multi precision shifts of 64 bits or more Operation COUNT COUNT MOD 32 SIZE OperandSize IF COUNT 0 THEN no operation ELSE IF COUNT SIZE THEN Bad parameters DEST is undefined CF OF SF ZF AF PF are ...

Page 370: ...bort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is ...

Page 371: ...ination operand For a 1 bit shift the OF flag is set if a sign change occurred otherwise it is cleared If the count operand is 0 the flags are not affected The SHRD instruction is useful for multiprecision shifts of 64 bits or more Operation COUNT COUNT MOD 32 SIZE OperandSize IF COUNT 0 THEN no operation ELSE IF COUNT SIZE THEN Bad parameters DEST is undefined CF OF SF ZF AF PF are undefined ELSE...

Page 372: ...lt Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment...

Page 373: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...

Page 374: ...ams Also this instruction can only be executed in protected mode Operation IF Itanium System Environment THEN IA 32_Intercept INST SLDT DEST LDTR SegmentSelector Flags Affected None Additional Itanium System Environment Exceptions IA 32_Intercept SLDT results in an IA 32 Intercept Protected Mode Exceptions GP 0 If the destination is located in a nonwritable segment If a memory operand effective ad...

Page 375: ...erence SLDT Store Local Descriptor Table Register Continued Real Address Mode Exceptions UD The SLDT instruction is not recognized in real address mode Virtual 8086 Mode Exceptions UD The SLDT instruction is not recognized in virtual 8086 mode ...

Page 376: ...286 processor programs and procedures intended to run on processors more recent than the Intel 286 should use the MOV control registers instruction to load the machine status word Operation IF Itanium System Environment THEN IA 32_Intercept INST SMSW DEST CR0 15 0 MachineStatusWord Flags Affected None Additional Itanium System Environment Exceptions IA 32_Intercept Mandatory Instruction Intercept ...

Page 377: ... If a memory operand effective address is outside the CS DS ES FS or GS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 378: ...STC Set Carry Flag Description Sets the CF flag in the EFLAGS register Operation CF 1 Flags Affected The CF flag is set The OF ZF SF AF and PF flags are unaffected Exceptions All Operating Modes None Opcode Instruction Description F9 STC Set CF flag ...

Page 379: ...e EFLAGS register When the DF flag is set to 1 string operations decrement the index registers ESI and or EDI Operation DF 1 Flags Affected The DF flag is set The CF OF ZF SF AF and PF flags are unaffected Operation DF 1 Exceptions All Operating Modes None Opcode Instruction Description FD STD Set DF flag ...

Page 380: ...LAG if The IF flag and the STI and CLI instruction have no affect on the generation of exceptions and NMI interrupts The following decision table indicates the action of the STI instruction bottom of the table depending on the processor s mode of operating and the CPL and IOPL of the currently running program or procedure top of the table Notes XDon t care NAction in Column 1 not taken YAction in ...

Page 381: ...L 3 THEN IF 1 ELSE IF CR4 VME 0 THEN GP 0 ELSE IF VIP 1 virtual interrupt is pending THEN GP 0 ELSE VIF 1 FI FI FI FI FI FI IF Itanium System Environment AND CFLG ii AND IF OLD_IF THEN IA 32_Intercept System_Flag STI Flags Affected The IF flag is set to 1 Additional Itanium System Environment Exceptions IA 32_Intercept System Flag Intercept Trap if CFLG ii is 1 and the IF flag changes state Protec...

Page 382: ... Instruction Reference 4 375 STI Set Interrupt Flag Continued Real Address Mode Exceptions None Virtual 8086 Mode Exceptions GP 0 If the CPL is greater has less privilege than the IOPL of the current program or procedure ...

Page 383: ...ag in the EFLAGS register If the DF flag is 0 the EDI register is incremented if the DF flag is 1 the EDI register is decremented The EDI register is incremented or decremented by 1 for byte operations by 2 for word operations or by 4 for doubleword operations The STOS STOSB STOSW and STOSD instructions can be preceded by the REP prefix for block loads of ECX bytes words or doublewords More often ...

Page 384: ...onwritable segment If a memory operand effective address is outside the limit of the ES segment If the ES register contains a null segment selector PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS...

Page 385: ...peration IF Itanium System Environment THEN IA 32_Intercept INST STR DEST TR SegmentSelector Flags Affected None Additional Itanium System Environment Exceptions IA 32_Intercept Mandatory Instruction Intercept Protected Mode Exceptions GP 0 If the destination is a memory operand that is located in a nonwritable segment or if the effective address is outside the CS DS ES FS or GS segment limit If t...

Page 386: ... result Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Opcode Instruction Descripti...

Page 387: ...ccurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside th...

Page 388: ...TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Opcode Instruction Description A8 ib TEST AL imm8 AND imm8 with AL set SF ZF PF according to result A9 iw TEST AX imm16 AND imm16 with AX set SF ZF PF according to result A9 id...

Page 389: ...ing is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment l...

Page 390: ...valid opcode exception this instruction is the same as the NOP instruction Operation IF Itanium System Environment THEN IA 32_Intercept INST 0F0B UD Generates invalid opcode exception Flags Affected None Additional Itanium System Environment Exceptions IA 32_Intercept Mandatory Instruction Intercept Exceptions All Operating Modes UD Instruction is guaranteed to raise an invalid opcode exception in...

Page 391: ...For the VERR instruction the segment must be readable the VERW instruction the segment must be a writable data segment If the segment is not a conforming code segment the segment s DPL must be greater than or equal to have less or the same privilege as both the CPL and the segment selector s RPL The validation performed is the same as if the segment were loaded into the DS ES FS or GS register and...

Page 392: ...Data Dirty Bit Fault Protected Mode Exceptions The only exceptions generated for these instructions are those related to illegal addressing of the source operand GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit If the DS ES FS or GS register is used to access memory and it contains a null segment selector SS 0 If a memory operand effective address is outsid...

Page 393: ...ny unmasked floating point exceptions the instruction may raise are handled before the processor can modify the instruction s results Operation CheckPendingUnmaskedFloatingPointExceptions FPU Flags Affected The C0 C1 C2 and C3 flags are undefined Floating point Exceptions None Protected Mode Exceptions NM MP and TS in CR0 is set Real Address Mode Exceptions NM MP and TS in CR0 is set Virtual 8086 ...

Page 394: ...ction When the processor is running in protected mode the CPL of a program or procedure must be 0 to execute this instruction This instruction is also a serializing instruction In situations where cache coherency with main memory is not a concern software can use the INVD instruction Operation IF Itanium System Environment THEN IA 32_Intercept INST WBINVD WriteBack InternalCaches Flush InternalCac...

Page 395: ...The WBINVD instruction cannot be executed at the virtual 8086 mode Intel Architecture Compatibility The WDINVD instruction implementation dependent its function may be implemented differently on future Intel architecture processors The instruction is not supported on Intel architecture processors earlier than the Intel486 processor ...

Page 396: ... Manual Volume 3 The MSRs control functions for testability execution tracing performance monitoring and machine check errors See model specific instructions for all the MSRs that can be written to with this instruction and their addresses The WRMSR instruction is a serializing instruction The CPUID instruction should be used to determine whether MSRs are supported EDX 5 1 before using this instru...

Page 397: ...on is not recognized in virtual 8086 mode Intel Architecture Compatibility The MSRs and the ability to read them with the WRMSR instruction were introduced into the Intel architecture with the Pentium processor Execution of this instruction by an Intel architecture processor earlier than the Pentium processor results in an invalid opcode exception UD ...

Page 398: ...y Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault IA 32_Intercept Lock Intercept If an external atomic bus lock is required to complete this operation and DCR lc is 1 no atomic transaction occurs this instruction is faulted and an IA 32_Intercept Lock fault is generated The software lock handler is responsible for the emulation of this instr...

Page 399: ...memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made Intel Architecture Compatibility Intel architecture processors earlier than the Intel486 processor do not recognize this instruc...

Page 400: ...of the BSWAP instruction for 16 bit operands Operation IF Itanium System Environment AND External_Atomic_Lock_Required AND DCR lc THEN IA 32_Intercept LOCK XCHG TEMP DEST DEST SRC SRC TEMP Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault D...

Page 401: ... or GS register contains a null segment selector SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS ...

Page 402: ...EBX ZeroExtend AL FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit F...

Page 403: ... segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 404: ...aults NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Opcode Instruction Description 34 ib XOR AL imm8 AL XOR imm8 35 iw XOR AX imm16 AX XOR imm16 35 id...

Page 405: ... occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS If a memory operand effective address is outside the SS segment limit Virtual 8086 Mode Exceptions GP 0 If a memory operand effective address is outside ...

Page 406: ... MMX Technology Instruction Reference 4 399 IA 32 Intel MMX Technology Instruction Reference 3 This section lists the IA 32 MMX technology instructions designed to increase performance of multimedia intensive applications ...

Page 407: ...subroutines that may execute floating point instructions If a floating point instruction loads one of the registers in the FPU register stack before the FPU tag word has been reset by the EMMS instruction a floating point stack overflow can occur that will result in a floating point exception or incorrect result Operation FPUTagWord FFFFH Flags Affected None Additional Itanium System Environment E...

Page 408: ...lue is written to the low order 32 bits of the 64 bit MMX technology register and zero extended to 64 bits see Figure 3 1 When the source operand is an MMX technology register the low order 32 bits of the MMX technology register are written to the 32 bit general purpose register or 32 bit memory location selected with the destination operand Operation IF DEST is MMX register THEN DEST ZeroExtend S...

Page 409: ...ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand...

Page 410: ...Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit...

Page 411: ...t occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outs...

Page 412: ...00H the saturated word value of 7FFFH or 8000H respectively is stored into the destination The destination operand for either the PACKSSWB or PACKSSDW instruction must be an MMX technology register the source operand may be either an MMX technology register or a quadword memory location Operation IF instruction is PACKSSWB THEN DEST 7 0 SaturateSignedWordToSignedByte DEST 15 0 DEST 15 8 SaturateSi...

Page 413: ...ata TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit UD If EM in CR0 is se...

Page 414: ... Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 415: ...rdToUnsignedByte DEST 47 32 DEST 31 24 SaturateSignedWordToUnsignedByte DEST 63 48 DEST 39 32 SaturateSignedWordToUnsignedByte SRC 15 0 DEST 47 40 SaturateSignedWordToUnsignedByte SRC 31 16 DEST 55 48 SaturateSignedWordToUnsignedByte SRC 47 32 DEST 63 56 SaturateSignedWordToUnsignedByte SRC 63 48 Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Re...

Page 416: ...alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effect...

Page 417: ...estination operand and therefore the result wraps around The PADDW instruction adds the words of the source operand to the words of the destination operand and stores the results to the destination operand When an individual result is too large to be represented in 16 bits the lower 16 bits of the result are written to the destination operand and therefore the result wraps around The PADDD instruc...

Page 418: ...C 15 8 DEST 23 16 DEST 23 16 SRC 23 16 DEST 31 24 DEST 31 24 SRC 31 24 DEST 39 32 DEST 39 32 SRC 39 32 DEST 47 40 DEST 47 40 SRC 47 40 DEST 55 48 DEST 55 48 SRC 55 48 DEST 63 56 DEST 63 56 SRC 63 56 ELSEIF instruction is PADDW THEN DEST 15 0 DEST 15 0 SRC 15 0 DEST 31 16 DEST 31 16 SRC 31 16 DEST 47 32 DEST 47 32 SRC 47 32 DEST 63 48 DEST 63 48 SRC 63 48 ELSE instruction is PADDD DEST 31 0 DEST 31...

Page 419: ...ment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective a...

Page 420: ...perand to the signed words of the destination operand and stores the results to the destination operand When an individual result is beyond the range of a signed word that is greater than 7FFFH or less than 8000H the saturated word value of 7FFFH or 8000H respectively is written to the destination operand Operation IF instruction is PADDSB THEN DEST 7 0 SaturateToSignedByte DEST 7 0 SRC 7 0 DEST 1...

Page 421: ...Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit UD If EM in CR0 is set NM If TS in ...

Page 422: ...rtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 423: ...he destination operand When an individual result is beyond the range of an unsigned byte that is greater than FFH the saturated unsigned byte value of FFH is written to the destination operand The PADDUSW instruction adds the unsigned words of the source operand to the unsigned words of the destination operand and stores the results to the destination operand When an individual result is beyond th...

Page 424: ...eToUnsignedWord DEST 47 32 SRC 47 32 DEST 63 48 SaturateToUnsignedWord DEST 63 48 SRC 63 48 FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumptio...

Page 425: ...pace from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligne...

Page 426: ...ted None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data ...

Page 427: ...hecking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address...

Page 428: ... must be an MMX technology register Operation DEST NOT DEST AND SRC Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault...

Page 429: ...t checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective addr...

Page 430: ...tion compares the words in the destination operand to the corresponding words in the source operand with the words in the destination operand being set according to the results The PCMPEQD instruction compares the doublewords in the destination operand to the corresponding doublewords in the source operand with the doublewords in the destination operand being set according to the results Opcode In...

Page 431: ...FFFFFFFFH ELSE DEST 31 0 0 IF DEST 63 32 SRC 63 32 THEN DEST 63 32 FFFFFFFFH ELSE DEST 63 32 0 FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consump...

Page 432: ...art of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault oc...

Page 433: ...results The PCMPGTW instruction compares the signed words in the destination operand to the corresponding signed words in the source operand with the words in the destination operand being set according to the results The PCMPGTD instruction compares the signed doublewords in the destination operand to the corresponding signed doublewords in the source operand with the doublewords in the destinati...

Page 434: ...nd third bytes in DEST and SRC IF DEST 63 48 SRC 63 48 THEN DEST 63 48 FFFFH ELSE DEST 63 48 0 ELSE instruction is PCMPGTD IF DEST 31 0 SRC 31 0 THEN DEST 31 0 FFFFFFFFH ELSE DEST 31 0 0 IF DEST 63 32 SRC 63 32 THEN DEST 63 32 FFFFFFFFH ELSE DEST 63 32 0 FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Registe...

Page 435: ... AC 0 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of t...

Page 436: ...000000H only when all four words of both the source and destination operands are 8000H Operation DEST 31 0 DEST 15 0 SRC 15 0 DEST 31 16 SRC 31 16 DEST 63 32 DEST 47 32 SRC 47 32 DEST 63 48 SRC 63 48 Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nest...

Page 437: ...gnment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective...

Page 438: ...7 32 SRC 47 32 DEST 63 48 HighOrderWord DEST 63 48 SRC 63 48 Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data K...

Page 439: ...ment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective a...

Page 440: ...OrderWord DEST 47 32 SRC 47 32 DEST 63 48 LowOrderWord DEST 63 48 SRC 63 48 Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Mi...

Page 441: ...ent checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective ad...

Page 442: ...Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit...

Page 443: ...t checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective addr...

Page 444: ...ination operand to the left by the number of bits specified in the count operand the PSLLD instruction shifts each of the two doublewords of the destination operand and the PSLLQ instruction shifts the 64 bit quadword in the destination operand As the individual data elements are shifted left the empty low order bit positions are filled with zeros Opcode Instruction Description 0F F1 r PSLLW mm mm...

Page 445: ...ternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit UD If EM in ...

Page 446: ...Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 447: ...ogy register a 64 bit memory location or an 8 bit immediate The PSRAW instruction shifts each of the four words in the destination operand to the right by the number of bits specified in the count operand the PSRAD instruction shifts each of the two doublewords in the destination operand As the individual data elements are shifted right the empty high order bit positions are filled with the sign v...

Page 448: ...ault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit UD If...

Page 449: ...irtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 450: ...words of the destination operand to the right by the number of bits specified in the count operand the PSRLD instruction shifts each of the two doublewords of the destination operand and the PSRLQ instruction shifts the 64 bit quadword in the destination operand As the individual data elements are shifted right the empty high order bit positions are filled with zeros Opcode Instruction Description...

Page 451: ...ternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a memory operand effective address is outside the CS DS ES FS or GS segment limit SS 0 If a memory operand effective address is outside the SS segment limit UD If EM in ...

Page 452: ...Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned memory reference is made ...

Page 453: ...n operand and therefore the result wraps around The PSUBW instruction subtracts the words of the source operand from the words of the destination operand and stores the results to the destination operand When an individual result is too large to be represented in 16 bits the lower 16 bits of the result are written to the destination operand and therefore the result wraps around The PSUBD instructi...

Page 454: ... SRC 15 8 DEST 23 16 DEST 23 16 SRC 23 16 DEST 31 24 DEST 31 24 SRC 31 24 DEST 39 32 DEST 39 32 SRC 39 32 DEST 47 40 DEST 47 40 SRC 47 40 DEST 55 48 DEST 55 48 SRC 55 48 DEST 63 56 DEST 63 56 SRC 63 56 ELSEIF instruction is PSUBW THEN DEST 15 0 DEST 15 0 SRC 15 0 DEST 31 16 DEST 31 16 SRC 31 16 DEST 47 32 DEST 47 32 SRC 47 32 DEST 63 48 DEST 63 48 SRC 63 48 ELSE instruction is PSUBD DEST 31 0 DEST...

Page 455: ...ignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effectiv...

Page 456: ...yond the range of a signed byte that is greater than 7FH or less than 80H the saturated byte value of 7FH or 80H respectively is written to the destination operand The PSUBSW instruction subtracts the signed words of the source operand from the signed words of the destination operand and stores the results to the destination operand When an individual result is beyond the range of a signed word th...

Page 457: ...d DEST 47 32 SRC 47 32 DEST 63 48 SaturateToSignedWord DEST 63 48 SRC 63 48 FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key...

Page 458: ...e from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligned m...

Page 459: ...and stores the results to the destination operand When an individual result is less than zero a negative value the saturated unsigned byte value of 00H is written to the destination operand The PSUBUSW instruction subtracts the unsigned words of the source operand from the unsigned words of the destination operand and stores the results to the destination operand When an individual result is less ...

Page 460: ...ateToUnsignedWord DEST 47 32 SRC 47 32 DEST 63 48 SaturateToUnsignedWord DEST 63 48 SRC 63 48 FI Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumpt...

Page 461: ... space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unalig...

Page 462: ... the destination operand and writes them to the destination operand The PUNPCKHDQ instruction interleaves the high order doubleword of the source operand and the high order doubleword of the destination operand and writes them to the destination operand If the source operand is all zeros the result stored in the destination operand contains zero extensions of the high order data elements from the ...

Page 463: ...ceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If...

Page 464: ...space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unalign...

Page 465: ...operand and writes them to the destination operand The PUNPCKLDQ instruction interleaves the low order doubleword of the source operand and the low order doubleword of the destination operand and writes them to the destination operand If the source operand is all zeros the result stored in the destination operand contains zero extensions of the high order data elements from the original value in t...

Page 466: ...ons Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Protected Mode Exceptions GP 0 If a me...

Page 467: ...pace from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception PF fault code If a page fault occurs AC 0 If alignment checking is enabled and an unaligne...

Page 468: ...T XOR SRC Flags Affected None Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Abort Itanium Mem FaultsVHPT Data Fault Nested TLB Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data A...

Page 469: ...ent checking is enabled and an unaligned memory reference is made while the current privilege level is 3 Real Address Mode Exceptions GP If any part of the operand lies outside of the effective address space from 0 to FFFFH UD If EM in CR0 is set NM If TS in CR0 is set MF If there is a pending FPU exception Virtual 8086 Mode Exceptions GP If any part of the operand lies outside of the effective ad...

Page 470: ...l MMX technology data types These include ability to stream data into and from the processor while minimizing pollution of the caches and the ability to prefetch data before it is actually used The main focus of packed floating point instructions is the acceleration of 3D geometry The new definition also contains additional SIMD Integer instructions to accelerate 3D rendering and video encoding an...

Page 471: ...E architecture is 100 compatible with the IEEE Standard 754 for Binary Floating point Arithmetic The SSE instructions are accessible from all IA execution modes Protected mode Real address mode and Virtual 8086 mode New Features The Intel SSE architecture provides the following new features while maintaining backward compatibility with all existing Intel architecture microprocessors IA application...

Page 472: ... is a new control status register MXCSR which is used to mask unmask numerical exception handling to set rounding modes to set flush to zero mode and to view status flags 4 6 Extended Instruction Set The Intel SSE architecture supplies a rich set of instructions that operate on either all or the least significant pairs of packed data operands in parallel The packed instructions operate on a pair o...

Page 473: ... floating point operands the upper three fields are passed through from the source operand Packed Scalar Multiplication and Division The MULPS Multiply packed single precision floating point instruction multiplies four pairs of packed single precision floating point operands The MULSS Multiply scalar single precision floating point instruction multiplies the least significant pair of packed single...

Page 474: ...MAXSS Maximum scalar single precision floating point instructions returns the maximum of the least significant pair of packed single precision floating point numbers into the destination register the upper three fields are passed through from the source operand to the destination register The MINPS Minimum packed single precision floating point instruction returns the minimum of each pair of packe...

Page 475: ...g point numbers and sets the ZF PF CF bits in the EFLAGS register the OF SF and AF bits are cleared The UCOMISS Unordered compare scalar single precision floating point ordered and set EFLAGS instruction compares the least significant pairs of packed single precision floating point numbers and sets the ZF PF CF bits in the EFLAGS register as described above the OF SF and AF bits are cleared 4 6 1 ...

Page 476: ... but only the low order 64 bits are utilized by the instruction 4 6 1 5 Conversion Instructions These instructions support packed and scalar conversions between 128 bit SSE registers and either 64 bit integer MMX technology registers or 32 bit integer IA 32 registers The packed versions behave identically to original MMX technology instructions in the presence of x87 FP instructions including Tran...

Page 477: ...uction converts the least significant single precision floating point number to a 32 bit signed integer in an Intel architecture 32 bit integer register when the conversion is inexact the rounded value according to the rounding mode in MXCSR is returned The CVTTSS2SI Convert truncate scalar single precision floating point to scalar 32 bit integer instruction is similar to CVTSS2SI except if the co...

Page 478: ...t by one bit position The high order bits of each element are filled with the carry bits of the sums To prevent cumulative round off errors an averaging is performed The low order bit of each final shifted result is set to 1 if at least one of the two least significant bits of the intermediate unshifted shifted sum is 1 The PEXTRW Extract 16 bit word from MMX technology register instruction moves ...

Page 479: ...s allow the programmer to prefetch data long before it s final use These instructions are not architectural since they do not update any architectural state and are specific to each implementation The programmer may have to tune his application for each implementation to take advantage of these instructions These instructions merely provide a hint to the hardware and they will not generate excepti...

Page 480: ...WC the transaction will be weakly ordered and is subject to all WC memory semantics The non temporal store will not write allocate Different implementations may choose to collapse and combine these stores In general WC semantics require software to ensure coherence with respect to other processors and other system agents such as graphics cards Appropriate use of synchronization and a fencing opera...

Page 481: ...oint values are represented identically both internally and in memory and are of the following form This is a change from x87 floating point which internally represents all numbers in 80 bit extended format This change implies that x87 FP libraries re written to use SSE instructions may not produce results that are identical to the those of the x87 FP implementation Real Numbers and Floating point...

Page 482: ... number has three parts a sign a significand and an exponent Figure 4 9 shows the binary floating point format that SSE data uses This format conforms to the IEEE standard The sign is a binary value that indicates whether the number is positive 0 or negative 1 The significand has two parts a 1 bit binary integer also referred to as the J bit and a binary fraction The J bit is often not represented...

Page 483: ...width To summarize a normalized real number consists of a normalized significand that represents a real number between 1 and 2 and an exponent that specifies the number s binary point 4 7 1 3 Biased Exponent The processor represents exponents in a biased form This means that a constant is added to the actual exponent so that the biased exponent is always a positive number The value of the biasing ...

Page 484: ...the type of computation being performed The following sections describe these number and non number classes 4 7 1 5 Signed Zeros Zero can be represented as a 0 or a 0 depending on the sign bit Both encodings are equal in value The sign of a zero result depends on the operation being performed and the rounding mode being used Signed zeros have been provided to aid in implementing interval arithmeti...

Page 485: ...on A denormalized number is computed through a technique called gradual underflow Table 4 2 gives an example of gradual underflow in the denormalization process Here the single real format is being used so the minimum exponent unbiased is 12610 The true result in this example requires an exponent of 12910 in order to have a normalized number Since 12910 is beyond the allowable exponent range the r...

Page 486: ...e of an infinity as a source operand constitutes an invalid operation Whereas denormalized numbers represent an underflow condition the two infinity numbers represent the result of an overflow condition Here the normalized result of a computation has a biased exponent greater than the largest allowable exponent for the selected result format 4 7 1 8 NaNs Since NaNs are non numbers they are not par...

Page 487: ... QNaN by setting the most significant fraction bit of the value to 1 The result is then stored in the destination operand and the invalid operation flag is set If the invalid operation mask is clear an invalid operation fault is signaled and no result is stored in the destination operand When a real operation or exception delivers a QNaN result the value of the result depends on the source operand...

Page 488: ...nge of this data type Only the fraction part of the significand is encoded The integer is assumed to be 1 for all numbers except 0 and denormalized finite numbers The exponent of the single precision data type is encoded in biased format The biasing constant is 127 for the single precision format Table 4 3 Results of Operations with NAN Operands Source Operands NaN Result invalid operation excepti...

Page 489: ...uctions There are sixty eight new instructions in SSE instruction set This chapter describes the packed and scalar floating point instructions in alphabetical order with a full description of each instruction The last two sections of this chapter describe the SIMD Integer instructions and the cacheability control instructions Table 4 4 Precision and Range of SSE Datatype Data Type Length Precision...

Page 490: ...ory operand Operand Size 66H Reserved and may result in unpredictable behavior Segment Override 2EH 36H 3EH 26H 64H 65H Affects SSE instructions with mem operand Ignored by SSE instructions without mem operand Repeat Prefix F3H Affects SSE instructions Repeat NE Prefix F2H Reserved and may result in unpredictable behavior Lock Prefix 0F0H Generates invalid opcode exception Table 4 7 SIMD Integer I...

Page 491: ...cified manner in which the processor handles this behavior and risks incompatibility with future processors 4 12 Notations Besides opcodes two kinds of notations are found which both describe information found in the ModR M byte 1 digit digit between 0 and 7 indicates that the instruction uses only the r m register and memory operand The reg field contains the digit that provides an extension to t...

Page 492: ...xing byte When there is ambiguity xmm1 indicates the first source operand and xmm2 the second source operand Table 4 9 describes the naming conventions used in the SSE instruction mnemonics Table 4 9 Key to SSE Naming Convention Mnemonic Description PI Packed integer qword e g mm0 PS Packed single FP e g xmm0 SI Scalar integer e g eax SS Scalar single FP e g low 32 bits of xmm0 ...

Page 493: ...for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCP...

Page 494: ...CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if C...

Page 495: ...ctive address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT...

Page 496: ...e address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Dat...

Page 497: ...g the comparison predicate specified by imm8 note that a subsequent computational instruction which uses this mask as an input operand will not generate a fault since a mask of all 0 s corresponds to a FP value of 0 0 and a mask of all 1 s corresponds to a FP value of qNaN Some of the comparisons can be achieved only through software emulation For these comparisons the programmer must swap the ope...

Page 498: ... is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault Predicate Descriptiona a The greater than greater than or equal not greater than and not greater than or equal relations...

Page 499: ... in hardware require more than one instruction to emulate in software and therefore should not be implemented as pseudo ops For these the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact Bits 7 4 of the immediate field are reserved...

Page 500: ...Note that a subsequent computational instruction which uses this mask as an input operand will not generate a fault since a mask of all 0 s corresponds to a FP value of 0 0 and a mask of all 1 s corresponds to a FP value of qNaN Some of the comparisons can be achieved only through software emulation For these comparisons the programmer must swap the operands copying registers when necessary to pro...

Page 501: ...XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode AC for unaligned memory reference if the current privilege level is 3 PF fault code for a page fault Predicate Descriptiona a The greater than greater than or ...

Page 502: ... in hardware require more than one instruction to emulate in software and therefore should not be implemented as pseudo ops For these the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact Bits 7 4 of the immediate field are reserved...

Page 503: ... 0 for an illegal address in the SS segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD i...

Page 504: ...Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments COMISS differs from UCOMISS in that it signals an invalid numeric exception when a source operand is either a qNaN or sNaN UCOMISS signals invalid only if a source operand is an sNaN The usage of Repeat F2H F3H and Operand Size 66H prefixes with COMISS is rese...

Page 505: ...n CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception AC for unaligned memory reference XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmaske...

Page 506: ...nent part of the corresponding x87 FP register However the use of a memory source operand with this instruction will not result in the above transition from x87 FP to MMX technology Prioritization for fault and assist behavior for CVTPI2PS is as follows Memory source 1 Invalid opcode CR0 EM 1 2 DNA CR0 TS 1 3 SS or GP for limit violation 4 PF page fault 5 SSE numeric fault i e precision Register s...

Page 507: ... if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OS...

Page 508: ...oritization for fault and assist behavior for CVTPS2PI is as follows Memory source 1 Invalid opcode CR0 EM 1 2 DNA CR0 TS 1 3 MF pending x87 FP fault signalled 4 After returning from MF x87 FP MMX technology transition 5 SS or GP for limit violation 6 PF page fault 7 SSE numeric fault i e invalid precision Register source 1 Invalid opcode CR0 EM 1 2 DNA CR0 TS 1 3 MF pending x87 FP fault signalled...

Page 509: ...c exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit...

Page 510: ... numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSF...

Page 511: ...SXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 ...

Page 512: ...e ones 1 s to the exponent part of the corresponding x87 FP register Prioritization for fault and assist behavior for CVTTPS2PI is as follows Memory source 1 Invalid opcode CR0 EM 1 2 DNA CR0 TS 1 3 MF pending x87 FP fault signalled 4 After returning from MF x87 FP MMX technology transition 5 SS or GP for limit violation 6 PF page fault 7 SSE numeric fault i e invalid precision Register source 1 I...

Page 513: ...SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 ...

Page 514: ...SE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 O...

Page 515: ...xception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 ...

Page 516: ...little endian byte order as arranged in memory with byte offset into row described by right column Opcode Instruction Description 0F AE 1 FXRSTOR m512byte Load FP Intel MMX technology and SSE state from m512byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rsrvd CS IP FOP FTW FSW FCW 0 Reserved MXCSR Rsrvd DS DP 16 Reserved ST0 MM0 32 Reserved ST1 MM1 48 Reserved ST2 MM2 64 Reserved ST3 MM3 80 Reserved S...

Page 517: ...rotection exception is signalled if the address is not aligned on 16 byte boundary Note that if AC is enabled and CPL is 3 signalling of AC is not guaranteed and may vary with implementation in all implementations where AC is not signalled a general protection fault will instead be signalled In addition the width of the alignment check when AC is enabled may also vary with implementation for insta...

Page 518: ...Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Notes State saved with FXSAVE and restored with FRSTOR and vice versa will result in incorrect restoration of state in the processor The address size prefix will have the usual effect on address calculation but will ...

Page 519: ...he state has been saved This instruction has been optimized to maximize floating point save performance The save data structure is as follows little endian byte order as arranged in memory with byte offset into row described by right column Opcode Instruction Description 0F AE 0 FXSAVE m512byte Store FP and Intel MMX technology state and SSE state to m512byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 520: ... TOS relative order which means that FR0 is always saved first followed by FR1 FR2 and so forth As an example if TOS 4 and only ST0 ST1 and ST2 are valid FSAVE saves the FTW field in the following format ST3 ST2 ST1 ST0 ST7 ST6 ST5 ST4 TOS 4 FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 11 xx xx xx 11 11 11 11 where xx is one of 00 01 10 11 indicates an empty stack elements and the 00 01 and 10 indicate Valid Z...

Page 521: ...on a 16 byte boundary FXSAVE generates a general protection exception FP Exceptions If AC exception detection is disabled a general protection exception is signalled if the address is not aligned on 16 byte boundary Note that if AC is enabled and CPL is 3 signalling of AC is not guaranteed and may vary with implementation in all implementations where AC is not signalled a general protection fault ...

Page 522: ...s Bit Fault Data Dirty Bit Fault Notes State saved with FXSAVE and restored with FRSTOR and vice versa will result in incorrect restoration of state in the processor The address size prefix will have the usual effect on address calculation but will have no effect on the format of the FXSAVE image If there is a pending unmasked FP exception at the time FXSAVE is executed the sequence of FXSAVE FWAI...

Page 523: ...ed These flags are cleared upon reset Bits 12 7 configure numerical exception masking an exception type is masked if the corresponding bit is set and it is unmasked if the bit is clear These enables are set upon reset meaning that all numerical exceptions are masked Bits 14 13 encode the rounding control which provides for the common round to nearest mode as well as directed rounding and true chop...

Page 524: ...d bit 6 are defined as reserved and cleared attempting to write a non zero value to these bits using either the FXRSTOR or LDMXCSR instructions will result in a general protection exception The linear address corresponds to the address of the least significant byte of the referenced memory data FP Exceptions General protection fault if reserved bits are loaded with non zero values Numeric Exceptio...

Page 525: ...TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments The usage of Repeat F2H F3H and Operand Size 66H prefixes with LDMXCSR is reserved Different processor implementations may handle this prefix differently Usage of this prefix with LDMXCSR risks incompati...

Page 526: ...d are both zeros source2 xmm2 m128 would be returned If source2 xmm2 m128 is an sNaN this sNaN is forwarded unchanged to the destination i e a quieted version of the sNaN is not returned FP Exceptions General protection exception if not aligned on 16 byte boundary regardless of segment Numeric Exceptions Invalid including qNaN source operand Denormal Protected Mode Exceptions GP 0 for an illegal m...

Page 527: ...Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments Note that if only one source is a NaN for these instructions the Src2 operand either NaN or real value is written to the result this differs from...

Page 528: ... in the SS segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 ...

Page 529: ...ne source is a NaN for these instructions the Src2 operand either NaN or real value is written to the result this differs from the behavior for other instructions as defined in Table 4 3 which is to always write the NaN to the result regardless of which source operand contains the NaN The upper three operands are still bypassed from the src1 operand as in all other scalar operations This approach ...

Page 530: ...red are both zeros source2 xmm2 m128 would be returned If source2 xmm2 m128 is an sNaN this sNaN is forwarded unchanged to the destination i e a quieted version of the sNaN is not returned FP Exceptions General protection exception if not aligned on 16 byte boundary regardless of segment Numeric Exceptions Invalid including qNaN source operand Denormal Protected Mode Exceptions GP 0 for an illegal...

Page 531: ...Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments Note that if only one source is a NaN for these instructions the Src2 operand either NaN or real value is written to the result this differs from...

Page 532: ...an illegal address in the SS segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID...

Page 533: ...ne source is a NaN for these instructions the Src2 operand either NaN or real value is written to the result this differs from the behavior for other instructions as defined in Table 4 3 which is to always write the NaN to the result regardless of which source operand contains the NaN The upper three operands are still bypassed from the src1 operand as in all other scalar operations This approach ...

Page 534: ...d memory data When a memory address is indicated the 16 bytes of data at memory location m128 are loaded or stored When the register register form of this operation is used the content of the 128 bit source register is copied into 128 bit destination register FP Exceptions General protection exception if not aligned on 16 byte boundary regardless of segment Numeric Exceptions None Opcode Instructi...

Page 535: ...stem Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments MOVAPS should be used when dealing with 16...

Page 536: ...l Address Mode Exceptions UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Comments The usage of Repeat F2H F3H and Operand Size 66H prefixes with MOVHLPS is reserved Diff...

Page 537: ...for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1...

Page 538: ...ts VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Comments The usage of Repeat Prefixes F2H F3H with MOVHPS is reserved Different processor implementations may handle this prefix differently Usage of this prefix with ...

Page 539: ...ess Mode Exceptions UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 Comments Example The usage of Repeat F2H F3H and Operand Size 66H prefixes with MOVLHPS is reserved Di...

Page 540: ...for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1...

Page 541: ...s VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Comments The usage of Repeat Prefixes F2H F3H with MOVLPS is reserved Different processor implementations may handle this prefix differently Usage of this prefix with M...

Page 542: ...f CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Comments T...

Page 543: ...xmm1 63 32 xmm1 63 32 xmm1 95 64 xmm1 95 64 xmm1 127 96 xmm1 127 96 else if destination m32 store instruction m32 xmm1 31 0 else move instruction xmm2 31 0 xmm1 31 0 xmm2 63 32 xmm2 63 32 xmm2 95 64 xmm2 95 64 Opcode Instruction Description F3 0F 10 r F3 0F 11 r MOVSS xmm1 xmm2 m32 MOVSS xmm2 m32 xmm1 Move 32 bits representing one scalar SP operand from XMM2 Mem to XMM1 register Move 32 bits repre...

Page 544: ...or unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CP...

Page 545: ...a When a memory address is indicated the 16 bytes of data at memory location m128 are loaded to the 128 bit multimedia register xmm or stored from the 128 bit multimedia register xmm When the register register form of this operation is used the content of the 128 bit source register is copied into 128 bit register xmm No assumption is made about alignment FP Exceptions None Numeric Exceptions None...

Page 546: ...e Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Comments MOVUPS should be used with SP FP numbers when that data is known to be unaligned The usage of this instruction should be limited to the cases where the aligned restriction is hard or impossible to meet SSE implementations gua...

Page 547: ...ic exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 Virtual 8086 Mode E...

Page 548: ... OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 Virtual 8086 Mode Exceptions Same e...

Page 549: ...effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault ...

Page 550: ...he operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data...

Page 551: ... 00000000000110000000001B 2126 The decimal approximations of the single precision numbers that delimit the three intervals specified above are as follows 1 11111111110100000000000B 2125 8 5039437 1037 1 11111111110100000000001B 2125 8 5039443 1037 1 00000000000110000000000B 2126 4 2550872 1037 1 00000000000110000000001B 2126 4 2550877 1037 The hexadecimal representations of the single precision nu...

Page 552: ...from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode AC for unaligned memory reference if the current privilege level is 3 PF fault code for a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data ...

Page 553: ... 00000000000110000000001B 2126 The decimal approximations of the single precision numbers that delimit the three intervals specified above are as follows 1 11111111110100000000000B 2125 8 5039437 1037 1 11111111110100000000001B 2125 8 5039443 1037 1 00000000000110000000000B 2126 4 2550872 1037 1 00000000000110000000001B 2126 4 2550877 1037 The hexadecimal representations of the single precision nu...

Page 554: ... is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault Add...

Page 555: ...C is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode AC for unaligned memory reference if the current privilege level is 3 PF fault code for a page fault Additional Itanium System E...

Page 556: ... 64 xmm2 m128 127 96 Description The SHUFPS instruction is able to shuffle any of the four SP FP numbers from xmm1 to the lower 2 destination fields the upper 2 destination fields are generated from a shuffle of any of the four SP FP numbers from xmm2 m128 By using the same register for both sources SHUFPS can return any combination of the four SP FP numbers from this register Bits 0 and 1 of the ...

Page 557: ...0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB...

Page 558: ...R4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CP...

Page 559: ...CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 V...

Page 560: ...is 3 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault AC for...

Page 561: ...ric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR b...

Page 562: ... CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 ...

Page 563: ...S segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 XM for an unmasked SSE numeric exception CR4 OSXMMEXCPT 1 UD for an unmasked SSE numeric exception CR4 OSXMMEXCPT 0 UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Addr...

Page 564: ...ent Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments UCOMISS differs from COMISS in that it signals an invalid numeric exception when a source operand is an sNaN COMISS signals invalid if a source operand is either a qNaN or an sNaN The usage of Repeat F2H F3H and Operand Size prefixes with UCOMISS is reserv...

Page 565: ...ctive address in the CS DS ES FS or GS segments SS 0 for an illegal address in the SS segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set ...

Page 566: ... Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments When unpacking from a memory operand an implementation may decide to fetch only the appropriate 64 bits Alignment to 16 byte boundary and normal segment checking will still be enforced The usage of Repeat Prefixes F2H F3H with UNPCKHPS is reserved Different p...

Page 567: ...ctive address in the CS DS ES FS or GS segments SS 0 for an illegal address in the SS segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set UD if CRCR4 OSFXSR bit 9 0 UD if CPUID XMM EDX bit 25 0 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set ...

Page 568: ... Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Comments When unpacking from a memory operand an implementation may decide to fetch only the appropriate 64 bits Alignment to 16 byte boundary and normal segment checking will still be enforced The usage of Repeat Prefixes F2H F3H with UNPCKLPS is reserved Different p...

Page 569: ...l 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key ...

Page 570: ...7 mm2 m64 63 56 for i 0 i 8 i temp i zero_ext x i 8 zero_ext y i 8 res i temp i 1 1 mm1 7 0 res 0 mm1 63 56 res 7 else if instruction PAVGW x 0 mm1 15 0 y 0 mm2 m64 15 0 x 1 mm1 31 16 y 1 mm2 m64 31 16 x 2 mm1 47 32 y 2 mm2 m64 47 32 x 3 mm1 63 48 y 3 mm2 m64 63 48 for i 0 i 4 i Opcode Instruction Description 0F E0 r PAVGB mm1 mm2 m64 Average with rounding packed unsigned bytes from MM2 Mem to pac...

Page 571: ...e CS DS ES FS or GS segments SS 0 for an illegal address in the SS segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would li...

Page 572: ...t PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode P...

Page 573: ...igned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception Virtual 8086 Mode Exceptions Same exceptions as in Real Add...

Page 574: ... enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code f...

Page 575: ...if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if the...

Page 576: ... enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code f...

Page 577: ...if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if the...

Page 578: ...it in CR0 is set MF if there is a pending FPU exception AC for unaligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU ex...

Page 579: ...tions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode PF fault code for a page fault ...

Page 580: ...is a MMX technology register The source operand can either be a MMX technology register or a 64 bit memory operand Numeric Exceptions None Protected Mode Exceptions GP 0 for an illegal memory operand effective address in the CS DS ES FS or GS segments SS 0 for an illegal address in the SS segment PF fault code for a page fault UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU ...

Page 581: ...or a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault ...

Page 582: ...ligned memory reference To enable AC exceptions three conditions must be true CR0 AM is set EFLAGS AC is set current CPL is 3 Real Address Mode Exceptions Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH UD if CR0 EM 1 NM if TS bit in CR0 is set MF if there is a pending FPU exception Virtual 8086 Mode Exceptions Same exceptions as in Real Ad...

Page 583: ...aults are signalled irrespective of the value of the mask Signalling of breakpoints code or data is not guaranteed different processor implementations may signal or not signal these breakpoints If the destination memory region is mapped as UC or WP enforcement of associated semantics for these memory types is not guaranteed i e is reserved and is implementation specific Dependency on the behavior ...

Page 584: ... unnecessary bandwidth since data is to be written directly using the byte mask without allocating old data prior to the store Similar to the SSE non temporal store instructions MASKMOVQ minimizes pollution of the cache hierarchy MASKMOVQ implicitly uses weakly ordered write combining stores WC See Section 4 6 1 9 Cacheability Control Instructions for further information about non temporal stores ...

Page 585: ...fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fault Data Key Permission Fault Data Access Rights Fault Data Access Bit Fault Data Dirty Bit Fault Com...

Page 586: ...Mode AC for unaligned memory reference if the current privilege level is 3 PF fault code for a page fault Additional Itanium System Environment Exceptions Itanium Reg Faults Disabled FP Register Fault if PSR dfl is 1 NaT Register Consumption Fault Itanium Mem Faults VHPT Data Fault Data TLB Fault Alternate Data TLB Fault Data Page Not Present Fault Data NaT Page Consumption Abort Data Key Miss Fau...

Page 587: ...dent It will however be a minimum of 32 bytes Prefetches to uncacheable memory UC or WC memory types will be ignored Additional ModRM encodings besides those specified above are defined to be reserved and the use of reserved encodings risks future incompatibility Numeric Exceptions None Protected Mode Exceptions None Real Address Mode Exceptions None Virtual 8086 Mode Exceptions None Additional It...

Page 588: ... As a result the SFENCE instruction provides a performance efficient way of ensuring ordering between routines that produce weakly ordered results and routines that consume this data SFENCE uses the following ModRM encoding Mod 7 6 11B Reg Opcode 5 3 111B R M 2 0 000B All other ModRM encodings are defined to be reserved and use of these encodings risks incompatibility with future processors Numeri...

Page 589: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...

Page 590: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...

Page 591: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...

Page 592: ... Fault 2 151 brl Instruction 3 30 brp Instruction 3 32 BSF Instruction 4 35 BSP RSE Backing Store Pointer Register 1 29 BSPSTORE RSE Backing Store Pointer for Memory Stores Register 1 30 BSR Instruction 4 37 bsw Instruction 3 34 BSWAP Instruction 4 39 BT Instruction 4 40 BTC Instruction 4 42 BTR Instruction 4 44 BTS Instruction 4 46 Bundle Format 1 38 Bundles 1 38 1 141 Byte Ordering 1 36 C CALL I...

Page 593: ...ER Instruction 4 94 EOI End of External Interrupt Register 2 124 epc Instruction 2 555 3 53 Epilog Count Register EC 1 33 Explicit Prefetch 1 70 External Controller Interrupts 2 96 External Interrupt 2 96 2 538 External Interrupt Control Registers CR64 81 2 42 External Interrupt Request Registers IRR0 3 2 125 External Interrupt Vector Register IVR 2 123 External Task Priority Cycle XTP 2 130 Exter...

Page 594: ...nstruction 3 93 FNSAVE Instruction 4 162 FNSTCW Instruction 4 176 FNSTENV Instruction 4 178 FNSTSW Instruction 4 180 for Instruction 3 94 fpabs Instruction 3 95 fpack Instruction 3 96 fpamax Instruction 3 97 fpamin Instruction 3 99 FPATAN Instruction 4 149 fpcmp Instruction 3 101 fpcvt Instruction 3 104 fpma Instruction 3 107 fpmax Instruction 3 109 fpmerge Instruction 3 111 fpmin Instruction 3 11...

Page 595: ...are Trap 2 232 IA 32 Interruption 2 111 IA 32 Interruption Vector Definitions 2 213 IA 32 Interruption Vector Descriptions 2 213 IA 32 Memory Ordering 2 265 IA 32 Physical Memory References 2 262 IA 32 SSE Extensions 1 20 1 130 IA 32 System Registers 2 246 IA 32 System Segment Registers 2 241 IA 32 Trap Code 2 213 IA 32 Virtual Memory References 2 261 IBR Index Breakpoint Register 2 151 2 152 IDIV...

Page 596: ...rruptions 2 95 2 537 Interrupts 2 96 2 114 External Interrupt Architecture 2 603 Interval Time Counter ITC 1 31 Interval Timer Match Register ITM 2 32 Interval Timer Offset ITO 2 34 Interval Timer Vector ITV 2 125 INTn Instruction 4 217 INTO Instruction 4 217 invala Instruction 3 146 INVD instructions 4 228 INVLPG Instruction 4 230 IP Instruction Pointer 1 27 1 140 IPI Inter processor Interrupt 2 ...

Page 597: ...a 2 615 MINPS Instruction 4 523 MINSS Instruction 4 525 mix Instruction 3 169 MMX technology 1 20 MOV Instruction 4 284 mov Instruction 3 172 MOVAPS Instruction 4 527 MOVD Instruction 4 401 MOVHLPS Instruction 4 529 MOVHPS Instruction 4 530 movl Instruction 3 187 MOVLHPS Instruction 4 532 MOVLPS Instruction 4 533 MOVMSKPS Instruction 4 535 MOVNTPS Instruction 4 578 MOVNTQ Instruction 4 579 MOVQ In...

Page 598: ...83 PAL_BRAND_INFO 2 366 PAL_BUS_GET_FEATURES 2 367 PAL_BUS_SET_FEATURES 2 369 PAL_CACHE_FLUSH 2 370 PAL_CACHE_INFO 2 374 PAL_CACHE_INIT 2 376 PAL_CACHE_LINE_INIT 2 377 PAL_CACHE_PROT_INFO 2 378 PAL_CACHE_READ 2 380 PAL_CACHE_SHARED_INFO 2 382 PAL_CACHE_SUMMARY 2 384 PAL_CACHE_WRITE 2 385 PAL_COPY_INFO 2 388 PAL_COPY_PAL 2 389 PAL_DEBUG_INFO 2 390 PAL_FIXED_ADDR 2 391 PAL_FREQ_BASE 2 392 PAL_FREQ_R...

Page 599: ...MINSW Instruction 4 569 PMINUB Instruction 4 570 PMOVMSKB Instruction 4 571 pmpy Instruction 3 213 pmpyshr Instruction 3 214 PMULHUW Instruction 4 572 PMULHW Instruction 4 431 PMULLW Instruction 4 433 PMV Performance Monitoring Vector 2 126 POP Instruction 4 311 POPA Instruction 4 315 POPAD Instruction 4 315 popcnt Instruction 3 216 POPF Instruction 4 317 POPFD Instruction 4 317 POR Instruction 4 ...

Page 600: ...on 4 337 REPNZ Instruction 4 337 REPZ Instruction 4 337 Reserved Variables 2 351 Reset Event 2 95 2 351 Resource Utilization Counter RUC 1 31 2 33 RET Instruction 4 340 rfi Instruction 2 543 3 236 RID Region Identifier 2 561 RNAT RSE NaT Collection Register 1 30 ROL Instruction 4 327 ROR Instruction 4 327 Rotating Registers 1 145 RR Region Register 2 58 2 561 RSC Register Stack Configuration Regis...

Page 601: ...ion Cache 2 49 2 567 Template Field Encoding 1 38 Templates 1 141 TEST Instruction 4 381 tf Instruction 3 263 thash Instruction 3 265 TLB Translation Lookaside Buffer 2 47 2 565 tnat Instruction 3 266 tpa Instruction 3 268 TPR Task Priority Register 2 123 2 605 TR Translation Register 2 48 2 566 Translation Cache TC 2 49 2 567 purge 2 568 Translation Instructions 2 60 Translation Lookaside Buffer ...

Page 602: ...ite Dependency 1 149 WRMSR Instruction 4 389 X XADD Instruction 4 391 XCHG Instruction 4 393 xchg Instruction 2 508 3 274 XLAT Instruction 4 395 XLATB Instruction 4 395 xma Instruction 3 276 xmpy Instruction 3 278 XOR Instruction 4 397 xor Instruction 3 279 XORPS Instruction 4 562 XTP External Task Priority Cycle 2 130 XTPR External Task Priority Register 2 605 Z zxt Instruction 3 280 ...

Page 603: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...

Page 604: ......

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