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Volume 2, Part 2: Memory Management
2:563
In a MAS OS, the RID bits act as an address space identifier or tag. For each
process-private region, a unique RID is assigned to that process by the OS. If a process
needs multiple process-private regions (e.g. the process requires a private 64-bit
address space), the OS assigns multiple unique RIDs for each such region. Because
each translation in the processor's TLBs is tagged with its RID, the TLBs may contain
translations from many different address spaces (RIDs) concurrently. This obviates the
need for the OS to purge the processor's TLBs upon an address space switch. When the
OS performs a context switch from process A to process B, the OS need only remove
process A's private RIDs from the CPU's region registers and replace them with process
B's private RIDs.
5.1.1.3
Cross-address Space Copies in a MAS OS
The use of regions, region registers, and RIDs provides a mechanism for efficient
address space-to-address space copies. Because translations are tied to RIDs and not
to a particular static region, a MAS OS can easily copy a memory range from one
address space to another by temporarily remapping the target memory location to
another region. This remapping is accomplished simply by placing the RID to which the
target location belongs into a different region register and then performing the copy
from source to target directly.
For example, assume a MAS OS wishes to copy and 8-byte buffer from virtual address
0x0000000000A00000 of the currently executing process (process A) to virtual address
0x0000000000A00000 of another process (process B):
movl r2 = (2 << 61)
mov r3 = process_b_rid
movl r4 = 0x0000000000A00000
movl r5 = 0x4000000000A00000;;;
// reference process B through RR[2]
mov rr[r2] = r3 ;;
// put process B RID into RR[2]
srlz.d
// serialize RR write
copyloop:
ld8 r6 = [r4] ;;
// read buffer from process A addr space
st8 [r5] = r6
// store buffer into process B addr
space
(p4)br copyloop
// loop until done
mov r3 = original_rr2_rid ;;
mov rr[r2] = r3 ;;
// restore RR[2] RID
srlz.d
// serialize RR write
When the OS switches to process B and places process B’s RID into RR[0] and resumes
execution of process B, the process can reference the message via virtual address
0x0000000000A00000. Note that no new translations need to be created to make the
sequence shown above work; because translations are tagged by RID and not by
region, all existing translations for process B’s address space are visible regardless of
which region the reference is made to, as long as the region register for that region
contains the correct process B RID. Note that the sequence shown above is intended for
illustrative purposes only; the OS may need to perform other steps as well to perform a
cross-address space copy.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...