Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 677 / 1898

Volume 2, Part 1: Processor Abstraction Layer 2:429
PAL_MC_ERROR_INJECT
Table 11-103. err_struct_info – Register File
Field Bits Description
siv 0 When 1, indicates that the structure information fields ( regfile_id, reg_num ) are valid and
should be used for error injection. When 0, the structure information fields are ignored,
and the values of these fields used for error injection are implementation-specific.
regfile_id 4:1 Identifies the register file where the error should be injected:
0 – Any register file type. When selected, the register file used for error injection is
determined by PAL.
1 – General register (bank0)(GR16-31)
2 – General register (bank1)(GR0-127)
3 – Floating point register
4 – Branch register
5 – Predicate register
6 – Application register
7 – Control register
8 – Region register
9 – Protection key register
10 – Data breakpoint register
11 – Instruction breakpoint register
12 – Performance monitor control register
13 – Performance monitor data register
All other values are reserved.
reg_num 12:5 Indicates the register number where the error should be injected. Procedure operation is
undefined if there is a conflict between the register number chosen for error injection,
and the registers being used by the procedure for code execution (see PAL calling
conventions, Section 11.9.2).
0-127: Specific register number corresponding to
regfile_id
128-254: Reserved for future use
255: Any register number. When selected, the actual register number used for error
injection is determined by PAL.
Reserved 31:13 Reserved
tiv 32 When 1, indicates that the trigger information fields ( trigger, trigger_pl ) are valid and
should be used for error injection. When 0, the trigger information fields are ignored and
error injection is performed immediately.
trigger 36:33 Indicates the operation type to be used as the error trigger condition. The address
corresponding to the trigger is specified in the trigger_addr field of the buffer pointed to
by err_data_buffer .
0 – Instruction memory access. The trigger match conditions for this operation type are
similar to the IBR address breakpoint match conditions as outlined in
Section 7.1.2,
“Debug Address Breakpoint Match Conditions” on page 2:154
1 – Data memory access. The trigger match conditions for this operation type are similar
to the DBR address breakpoint match conditions as outlined in
Section 7.1.2, “Debug
Address Breakpoint Match Conditions” on page 2:154 .
All other values are reserved.
trigger_pl 39:37 Indicates the privilege level of the context during which the error should be injected:
0 – privilege level 0
1 – privilege level 1
2 – privilege level 2
3 – privilege level 3
All other values are reserved.
If the implementation does not support privilege level qualifier for triggers (i.e. if
trigger_pl is 0 in the capabilities vector), this field is ignored and triggers can be taken at
any privilege level.
Reserved 63:40 Reserved