Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 561 / 1898

Volume 2, Part 1: Processor Abstraction Layer 2:313
• BR0 PAL PMI return address.
• ARs: The contents of all application registers are unchanged from the time of the
interruption, except the RSE control register (RSC) and the ITC and RUC counters.
The RSC.mode field will be set to 0 (enforced lazy mode) while the other fields in
the RSC are unchanged. The ITC register will not be directly modified by PAL, but
will continue to count during the execution of the PMI handler. The RUC register will
not be directly modified by PAL, but will continue to count during the execution of
the PMI handler while the processor is active.
• CFM: The contents of the CFM register is unchanged from the time of the
interruption.
• RSE: Is in enforced lazy mode, and stacked registers are unchanged from the time
of the interruption.
• PSR: PSR.mc, PSR.mfl, PSR.mfh, and PSR.pk are unchanged; all other bits are 0.
• CRs: The contents of all control registers are unchanged from the time of the
interruption with the exception of interruption resources, which are described
below.
• RRs: The contents of all region registers are unchanged from the time of the
interruption.
• PKRs: The contents of all protection key registers are unchanged from the time of
the interruption.
• DBR/IBRs: The contents of all breakpoint registers are unchanged from the time of
the interruption.
• PMCs/PMDs: The contents of the PMC registers are unchanged from the time of the
PMI. The contents of the PMD registers are not modified by PAL code, but may be
modified if events it is monitoring are encountered
• Cache: The processor internal cache is not specifically modified by the PMI handler
but may be modified due to normal cache activity of running the handler code.
• TLB: The TCs are not modified by the PALE_PMI handler and the TRs are unchanged
from the time of the interruption.
• Interruption Resources:
• IRRs: The contents of IRRs are unchanged from the time of the interruption.
• IIP and IPSR contain the value of IP and PSR. The IFS.v bit is reset to 0.
11.5.3 Resume from the PMI Handler
To return to the instruction that was interrupted by the PMI event, SAL PMI must
branch to the PAL PMI target address in BR0. All register contents must be preserved as
specified in
Section 11.5.2, “PALE_PMI Exit State” on page 2:312 .
11.6 Power Management
This section describes the architecturally supported set of required and optional power
states that may be implemented to reduce power consumption in implementations
where this is a design goal. In addition, the PAL interfaces required to manage these
states are described.