Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 388 / 1898

2:140 Volume 2, Part 1: Register Stack Engine
Protection is also checked based on the current entries in the data TLB. The RSE always
remains coherent with respect to the data TLB. If a translation that is being used by the
RSE is changed or purged, the RSE will immediately begin using the new translation or
suffer a TLB miss. Only mandatory loads and stores can cause RSE memory related
faults. Details on RSE fault delivery are described in
“RSE Interruptions” Although eager
RSE loads and stores do not cause interruptions they can, under certain conditions,
cause a VHPT walk and TLB insert. Details on when RSE loads and stores can cause a
VHPT walk are described in
“VHPT Environment” on page 2:67 .
The RSE expects its backing store to be mapped to cacheable speculative memory. If
RSE spill/fill transactions are performed to non-speculative memory that may contain
I/O devices, system behavior is unpredictable.
RSE Byte Order: Because the RSE runs asynchronously with the processor, it may be
running on behalf of a context with a different byte order from the current one.
Consequently, the RSE defines its own byte ordering bit: RSC.be. When RSC.be is zero,
registers are stored in little-endian byte order (least significant bytes to lower
addresses). When RSC.be is one, registers are stored in big-endian byte order (most
significant bytes to lower addresses). RSC.be also determines the byte order of NaT
collections spilled/filled by the RSE. RSC.be may be written by code at any privilege
level. Changes to RSC.be should only be made by software when RSC.mode is zero.
Failure to do so results in undefined backing store contents.
6.5.2 Register Stack NaT Collection Register
As described in Section 6.1, “RSE and Backing Store Overview” on page 2:133 , the RSE
is responsible for saving and restoring NaT bits associated with the stacked registers to
and from the backing store. The RSE writes its NaT collection register (the RNAT
application register) to the backing store whenever BSPSTORE{8:3} = 0x3F (1 NaT
collection for every 63 registers). The RNAT acts as a temporary holding area for up to
63 unsaved NaT bits. The RSE NaT collection bit index (RSE.RNATBitIndex) determines
which bit of the RNAT register receives the NaT bit of a spilled register as the result of
an RSE store. The six-bit wide RSE.RNATBitIndex is always equal to BSPSTORE{8:3}.
As a result, RNAT{
x
} corresponds to the register saved at
concatenate(BSPSTORE{63:9},x{5:0},0{2:0}).
The RSE never saves partial NaT collections to the backing store, so software must save
and restore the RNAT application register when switching the backing store pointer.
RSE.RNATBitIndex determines which RNAT bits are valid. Bits
RNAT{RSE.RNATBitIndex:0} contain defined values, and bits
RNAT{62:RSE.RNATB1} contain undefined values. Bit 63 of the RNAT
application register always reads as zero. Writes to bit 63 of the RNAT application
register are ignored. The execution of RSE control instructions
mov
to BSPSTORE and
loadrs
as well as an RSE spill of the RNAT register cause the contents of the RNAT
register to become undefined. The RNAT application register can only be accessed when
RSC.mode is zero. If RSC.mode is non-zero, accessing the RNAT application register
results in an Illegal Operation fault.