Volume 4: IA-32 SSE Instruction Reference
4:463
IA-32 SSE Instruction Reference
4
4.1
IA-32 SSE Instructions
This section lists the IA-32 SSE instructions designed to increase performance of IA-32
3D and floating-point intensive applications. For details on SSE please refer to the
Intel
®
64 and IA-32 Architectures Software Developer’s Manual
.
4.2
About the Intel
®
SSE Architecture
The Intel SSE architecture accelerates performance of 3D graphics applications over the
current P6 generation of the Pentium Pro, Pentium II and Pentium
III
processors. The
programming model is similar to the MMX technology model except that instructions
now operate on new packed floating-point data types which contain four
single-precision floating-point numbers.
The Intel SSE architecture introduces new general purpose floating-point instructions,
which operate on a new set of eight 128-bit SSE registers. This gives the programmer
the ability to develop algorithms that can finely mix packed single-precision
floating-point and integer using both SSE and MMX technology instructions respectively.
In addition to these instructions, the Intel SSE architecture also provides new
instructions to control cacheability of all MMX technology data types. These include
ability to stream data into and from the processor while minimizing pollution of the
caches and the ability to prefetch data before it is actually used. The main focus of
packed floating-point instructions is the acceleration of 3D geometry. The new definition
also contains additional SIMD Integer instructions to accelerate 3D rendering and video
encoding and decoding. Together with the cacheability control instruction, this
combination enables the development of new algorithms that can significantly
accelerate 3D graphics.
The new SSE state requires OS support for saving and restoring the new state during a
context switch. A new set of extended FSAVE/FRSTOR instructions will permit
saving/restoring new and existing state for applications and OS. To make use of these
new instructions, an application must verify that the processor supports the Intel SSE
architecture and the operating system supports this new extension. If both the
extension and support is enabled, then the software application can use the new
features.
The SSE instruction set is fully compatible with all software written for Intel architecture
microprocessors. All existing software continues to run correctly, without modification,
on microprocessors that incorporate the Intel SSE architecture, as well as in the
presence of existing and new applications that incorporate this technology.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...