Intel Itanium 9150M, Manual

Page: 346 / 420

Volume 3: Instruction Formats 3:337
4.4.1.12 Floating-point Load Pair – Increment by Immediate
M12
4.4.2 Line Prefetch
The line prefetch instructions are encoded in major opcodes 6 and 7 along with the
floating-point load/store instructions. See
“Loads and Stores” on page 3:323 for a
summary of the opcode extensions.
The line prefetch instructions all have a 2-bit cache locality opcode hint extension field
in bits 29:28 (hint) as shown in
Table 4-44 .
40 37 36 35 30 29 28 27 26 20 19 13 12 6 5 0
6 m x
6
hint x r
3
f
2
f
1
qp
4 1 6 2 1 7 7 7 6
Instruction Operands Opcode
Extension
m x x
6
hint
ldfps. ldhint f
1
, f
2
= [ r
3
], 8
6 1 1
02
See Table 4-39
on page 3:328
ldfpd. ldhint
f
1
, f
2
= [ r
3
], 16
03
ldfp8. ldhint 01
ldfps.s. ldhint f
1
, f
2
= [ r
3
], 8 06
ldfpd.s. ldhint
f
1
, f
2
= [ r
3
], 16
07
ldfp8.s. ldhint 05
ldfps.a. ldhint f
1
, f
2
= [ r
3
], 8 0A
ldfpd.a. ldhint
f
1
, f
2
= [ r
3
], 16
0B
ldfp8.a. ldhint 09
ldfps.sa. ldhint f
1
, f
2
= [ r
3
], 8 0E
ldfpd.sa. ldhint
f
1
, f
2
= [ r
3
], 16
0F
ldfp8.sa. ldhint 0D
ldfps.c.clr. ldhint f
1
, f
2
= [ r
3
], 8 22
ldfpd.c.clr. ldhint
f
1
, f
2
= [ r
3
], 16
23
ldfp8.c.clr. ldhint 21
ldfps.c.nc. ldhint f
1
, f
2
= [ r
3
], 8 26
ldfpd.c.nc. ldhint
f
1
, f
2
= [ r
3
], 16
27
ldfp8.c.nc. ldhint 25
Table 4-41. Line Prefetch Hint Completer
hint
Bits 29:28
lfhint
0 none
1 .nt1
2 .nt2
3 .nta