Intel Itanium 9150M, Manual

Page: 285 / 420

3:276 Volume 3: Instruction Reference
xma
xma — Fixed-Point Multiply Add
Format: (
qp
) xma.l
f
1
=
f
3
,
f
4,
f
2
low_form F2
(
qp
) xma.lu
f
1
=
f
3
,
f
4,
f
2
pseudo-op of: (
qp
) xma.l
f
1
=
f
3
,
f
4
,
f
2
(
qp
) xma.h
f
1
=
f
3
,
f
4,
f
2
high_form F2
(
qp
) xma.hu
f
1
=
f
3
,
f
4,
f
2
high_unsigned_form F2
Description:
Two source operands (FR
f
3
and FR
f
4
) are treated as either signed or unsigned integers
and multiplied. The third source operand (FR
f
2
) is zero extended and added to the
product. The upper or lower 64 bits of the resultant sum are selected and placed in FR
f
1
.
In the high_unsigned_form, the significand fields of FR
f
3
and FR
f
4
are treated as
unsigned integers and multiplied to produce a full 128-bit unsigned result. The
significand field of FR
f
2
is zero extended and added to the product. The most significant
64-bits of the resultant sum are placed in the significand field of FR
f
1
.
In the high_form, the significand fields of FR
f
3
and FR
f
4
are treated as signed integers
and multiplied to produce a full 128-bit signed result. The significand field of FR
f
2
is
zero extended and added to the product. The most significant 64-bits of the resultant
sum are placed in the significand field of FR
f
1
.
In the other forms, the significand fields of FR
f
3
and FR
f
4
are treated as signed integers
and multiplied to produce a full 128-bit signed result. The significand field of FR
f
2
is
zero extended and added to the product. The least significant 64-bits of the resultant
sum are placed in the significand field of FR
f
1
.
In all forms, the exponent field of FR
f
1
is set to the biased exponent for 2.0
63
(0x1003E) and the sign field of FR
f
1
is set to positive (0).
Note: f1 as an operand is not an integer 1; it is just the register file format’s 1.0
value.
In all forms, if any of FR
f
3
, FR
f
4
, or FR
f
2
is a NaTVal, FR
f
1
is set to NaTVal instead of
the computed result.