Volume 3: Instruction Reference
3:273
vmsw
vmsw — Virtual Machine Switch
Format:
vmsw.0
zero_form
vmsw.1
one_form
Description:
This instruction sets the PSR.vm bit to the specified value. This instruction can be used
to implement transitions to/from virtual machine mode without the overhead of an
interruption.
If instruction address translation is enabled and the page containing the
vmsw
instruction has access rights equal to 7, then the new value is written to the PSR.vm
bit. In the zero_form, PSR.vm is set to 0, and in the one_form, PSR.vm is set to 1.
Instructions after the
vmsw
instruction in the same instruction group may be executed
with the old or new value of PSR.vm. Instructions in subsequent instruction groups will
be executed with PSR.vm equal to the new value.
If the above conditions are not met, this instruction takes a Virtualization fault.
This instruction can only be executed at the most privileged level. This instruction
cannot be predicated.
Implementation of PSR.vm is optional. If it is not implemented, this instruction takes
Illegal Operation fault. If it is implemented but either virtual machine features or the
vmsw
instruction are disabled, this instruction takes Virtualization fault when executed
at the most privileged level.
Operation:
if (!implemented_vm())
illegal_operation fault();
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (!(PSR.it == 1 && itlb_ar() == 7) || vm_disabled() || vmsw_disabled())
virtualization_fault();
if (zero_form) {
PSR.vm = 0;
}
else {
PSR.vm = 1;
}
Interruptions:
Illegal Operation fault
Virtualization fault
Privileged Operation fault
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
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