Intel Itanium 9150M, Manual

Page: 268 / 420

Volume 3: Instruction Reference 3:259
sync
sync — Memory Synchronization
Format: (
qp
) sync.i M24
Description: sync.i
ensures that when previously initiated Flush Cache (
fc
,
fc.i
) operations issued
by the local processor become visible to local data memory references, prior Flush
Cache operations are also observed by the local processor instruction fetch stream.
sync.i
also ensures that at the time previously initiated Flush Cache (
fc
,
fc.i
)
operations are observed on a remote processor by data memory references they are
also observed by instruction memory references on the remote processor.
sync.i
is
ordered with respect to all cache flush operations as observed by another processor. A
sync.i
and a previous
fc
must be in separate instruction groups. If semantically
required, the programmer must explicitly insert ordered data references (acquire,
release or fence type) to appropriately constrain
sync.i
(and hence
fc
and
fc.i
)
visibility to the data stream on other processors.
sync.i
is used to maintain an ordering relationship between instruction and data
caches on local and remote processors. An instruction serialize operation must be used
to ensure synchronization initiated by
sync.i
on the local processor has been observed
by a given point in program execution.
An example of self-modifying code (local processor):
st [L1] = data //store into local instruction stream
fc.i L1 //flush stale datum from instruction/data cache
;; //require instruction boundary between fc.i and sync.i
sync.i //ensure local and remote data/inst caches
//are synchronized
;;
srlz.i //ensure sync has been observed by the local processor,
;; //ensure subsequent instructions observe
//modified memory
L1: target //instruction modified
Operation: if (PR[ qp ]) {
instruction_synchronize();
}
Interruptions:
None