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3:138
Volume 3: Instruction Reference
fswap
Operation:
if (PR[
qp
]) {
fp_check_target_register(
f
1
);
if (tmp_isrcode = fp_reg_disabled(
f
1
,
f
2
,
f
3
, 0))
disabled_fp_register_fault(tmp_isrcode, 0);
if (fp_is_natval(FR[
f
2
]) || fp_is_natval(FR[
f
3
])) {
FR[
f
1
] = NATVAL;
} else {
if (swap_form) {
tmp_res_hi = FR[
f
3
].significand{31:0};
tmp_res_lo = FR[
f
2
].significand{63:32};
} else if (swap_nl_form) {
tmp_res_hi = (!FR[
f
3
].significand{31} << 31)
| (FR[
f
3
].significand{30:0});
tmp_res_lo = FR[
f
2
].significand{63:32};
} else { // swap_nr_form
tmp_res_hi = FR[
f
3
].significand{31:0};
tmp_res_lo = (!FR[
f
2
].significand{63} << 31)
| (FR[
f
2
].significand{62:32});
}
FR[
f
1
].significand = fp_concatenate(tmp_res_hi, tmp_res_lo);
FR[
f
1
].exponent = FP_INTEGER_EXP;
FR[
f
1
].sign = FP_SIGN_POSITIVE;
}
fp_update_psr(
f
1
);
}
FP Exceptions:
None
Interruptions:
Illegal Operation fault
Disabled Floating-point Register fault
Figure 2-20. Floating-point Swap Negate Right
81
0
80
64
81
0
80
64 63
81
0
80
64 63
FR
f
2
FR
f
3
FR
f
1
31
32
0
1003E
31
32 31
Negated Sign Bit
62
30
63
32
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......