Intel iSBC 546 Hardware Reference Manual Download Page 1

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Summary of Contents for iSBC 546

Page 1: ...48 HIGH PERFORMANCE TERMINAL CONTROLLERS HARDWARE REFERENCE MANUAL Order Number 122704 001 Copyright 1986 Intel Corporation All Rights Reserved I Intel Corporation 3065 Bowers Avenue Santa Clara Calif...

Page 2: ...ed in any form or by any means without prior written consent of Intel Corporation Intel Corporation makes no warranty for the usc of its products and assumes no responsibility for any errors which may...

Page 3: ...REV REVISION HISTORY DATE 001 Original Issue 2 86 iii tv...

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Page 5: ...s of the boards Chapter 3 provides the information required to install the board Programming information is provided in Chapter 4 as well as in Appendix A and B Connector pin out information for all b...

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Page 7: ...tional Description 2 4 CHAPTER 3 INSTALLATION 3 1 Introduction 3 1 3 2 Unpacking And Inspection 3 l 3 3 Compatible Equipment 3 l 3 4 Installation Considerations 3 2 3 4 1 Connector Configurations 3 2...

Page 8: ...roduction B 1 B 2 Firmware Overvie iliT B 1 B 2 1 Firmware Operation B 4 B 2 2 Recommendations For High Performance B 5 B 3 Functional Architecture B 6 B 3 1 structures of Dual Ported RAM B 6 B 3 1 1...

Page 9: ...Diagram 1 2 iSBC 548 High Performance Terminal Controller 1 6 1 3 iSBC 547 High Performance Terminal Controller 1 6 1 4 iSBC 548 High Performance Terminal Controller 1 7 2 1 iSBC 547 and iSBC 548 Fun...

Page 10: ...lear DSR Report Message Format B 29 Set RI Report Message Format B 3 0 Clear RI Report Message Format B 31 Clear DTR Message Format B 32 Set Break Message Format B 3 3 Clear Break Message Format B 34...

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Page 12: ...the key features a brief description of each board and a list of specifications 1 2 BOARD FEATURES This section provides a brief list of key features of the iSBC 548 and iSBC 547 boards o Eight Mhz 8...

Page 13: ...el 80186 microprocessor operating at 8 Mhz as its cpu The 80186 controls eight serial channels sending data to or receiving data from the MUL TIBUS host The on board 80186 gains the attention of the M...

Page 14: ...et an interrupt to the MULTIBUS host generated by the board The eight serial interfaces on the iSBC 547 board are through eight 9 pin connectors The 9 pin connections are fully compatible with the IBM...

Page 15: ...s are fully compatible with the IBM PCAT connections The line printer interface is compatible with the IBM line printer interface The iSBC 546 board has two on board 82530 Serial Communications Contro...

Page 16: ...546 ONLY I I Figure 1 1 GENERAL INFORMATION 5 REFRESH LOGIC ALL BOARDS REFRESH CONTROL SIGNALS MULTIBUS RAM ALL BOARDS IRAM CONTROL SIGNALS RAM CONTROL ALL BOARDS 80186 MICROPROCESSOR ALL BOARDS L ___...

Page 17: ...C Figure 1 3 iSBC GENERAL INFORMATION PIN 39 TOP PIN 40 BOTTOM SERIAL CONNECTOR J1 PIN 1 TOP PIN2 BOTTOM MULTIBUS CONNECTOR P2 PIN 39 TOP PIN 40 BOTTOM SERIAL CONNECTOR J2 548 High Performance Termina...

Page 18: ...iSBC GENERAL INFORMATION PRINTER INTERFACE CONNECTOR J5 MULTIBUS CONNECTOR P1 SERIAL CONNECTOR J4 SERIAL CONNECTOR J3 SERIAL CONNECTOR J2 MULTIBUS GONNECTOR P2 548 High Performance Terminal Controlle...

Page 19: ...nsfer rate per channel 19 2K Baud Typical performance with firmware is 96K Baud Four RS232C channels DTE configured Maximum transfer rate per channel 19 2K Baud MULTIBUS connectors PI and P2 All MUL I...

Page 20: ...the board requires an INIT pulse of at least 50 microseconds duration Eight RS232C channels eight 9 pin connectors MULTIBUS connectors Pl and P2 All MULTIBUS signals supported At power up the board re...

Page 21: ...ions Summary continued Physical Dimensions width Length iSBC 546 1 2 00 in 30 48 cm 10 00 in 25 40 cm Height Including Components 0 50 in 1 27 cm 1 10 iSBC 547 iSBC 548 12 00 in 12 00 in 30 48 cm 30 4...

Page 22: ...0th boards use an Intel 80186 microprocessor operating at 8 Mhz as their main processors The 80186 has a 16 bit data bus and 16 bit internal architecture The 80186 provides all bus controls without th...

Page 23: ...E EIGHT SERIAL CHANNELS OF THE ISSC 548 ARE BROUGHT OUT THROUGH TWO 40 PIN CONNECTORS Figure 2 1 IOB IOB7 I O BUFFER iSBC BOARD OPERATION 80186 PROCESSOR C ______M_V_L T B_V_S_ _ ___ J SELMBL HOST REF...

Page 24: ...two Intel 2764 EPROMs which contain the controller firmware Appendix B of this manual describes the firmware in dl tail Although the controller boards are supplied with 2764 EPROMs the boards can supp...

Page 25: ...s It differs primarily in that it has a line printer interface connector and associated circuitry a clock calendar circuit and supports only four serial channels The iSBC 546 processes data in the sam...

Page 26: ...de Coding of the two bits is as follows Function PC4 PC5 Output to Clock Mode 1 0 Input From Clock Mode 0 1 Reset LP and Clock 1 1 Interface Reset Clock Interface 0 0 Only 1 1henever a new clock set i...

Page 27: ...OB7 ClKBUSO CLKBUS7 CLOCK AND CALENDER CKT 110 BUFFER r ADO AD 80186 PROCESSOR ADO I 015 SELMBL HOS T REFRESH LOGIC RAS CAS r AAMCONTROL AND ARBITRATION LOGIC WRl WRH LOC DEW 1 ADO AD15 RAM BUFFERS MU...

Page 28: ...the carrier s agent be present when the carton is opened If the carrier s agent is not present when the carton is opened and the contents are damaged keep the carton and packing material for the agent...

Page 29: ...the boards are grouped so that several boards share the same I O address and the same interrupt line The boards however cannot share the same address space As an example if a system has one unused in...

Page 30: ...for pin assignments connector J5 is the printer interface connector see Table 5 7 for pin assignments and Table 5 8 for signal descriptions 3 4 2 BATTERY BACKUP In order to use the battery backup for...

Page 31: ...ULTIBUS CONNECTOR P1 Figure 3 1 PIN 39 TOP PIN 40 BOTTOM iSBC INSTALLATION PIN 1 TOP PIN2 SERIAL CONNECTOR J1 BOTTOM MULTIBUS CONNECTOR P2 PIN 39 TOP PIN 40 BOTTOM 548 Board Connector Locations 3 4 SE...

Page 32: ...Figure 3 2 MULTIBUS CONNECTOR Pl iSBC INSTALLATION SERIAL CIHANNEL CONNECTORS MULTIBUS CONNECTOR P2 547 Board Connector Locations 3 5 2342...

Page 33: ...2341 The iSBC 548 board requires two flat 40 conductor cables to connect to the back panel These cables can be acquired from Intel as part of the Intel 310 Cable Kit or can be fabricated by the user T...

Page 34: ...40 with strain relief T B Ansley 609 4000M without strain relief T B Ansley 609 400lM with strain relief T B Ansley 609 9P ML metal shroud male Table 3 2 Pin to Pin wiring List 40 Pin P4 P3 40 Pin P2...

Page 35: ...iSBC 548 COMPONENT SIDE INSTALLATION EACH 9 CONDUCTOR LENGTH IS 5 INCHES LAST FOUR PINS OPEN 40 PIN MALE CONNECTOR r 5 BOTTOM 2334 Figure 3 4 iSBC 548 RS232C Cable Construction 3 8...

Page 36: ...1 Check Appendix A for the jumper configuration 2 Ensure that power to your system is turned off 3 For the iSBC 548 board install the I O cables to the 40 pin connectors 4 Install the terminal control...

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Page 38: ...e been installed by the factory the default condition or to install his own configuration 4 3 ADDRESSING Figure 4 1 is a memory map for the iSBC 546 547 548 controllers The controller boards include t...

Page 39: ...S 12BK Bytes On Board Memory 16 32 64 K Bytes EPROM 64K Bytes Dual Port RAM RAM MULTIBUS FFBOOO H 32K Bytes FSOOOO H OFFFFF H I r 32K Bytes OSOOOO H ______ NOTE Dual ported RAM can be accessed on the...

Page 40: ...ief description of firmware operation The 80186 microprocessors on the iSBC 547 and iSBC 548 boards control eight serial data channels The 80186 on the iSBC 546 controls four serial data channels The...

Page 41: ...547 and 548 boards and line printer interface and clock calendar on the iSBC 546 board Selects serial ports 7 and 8 iSBC 547 and 548 only sets MULTIBUS interrupt port when used as an output PCS5 is no...

Page 42: ...erial Line 6 control or I O Line Printer 0 serial Line 6 I O data or clock calendar Serial Line 5 I O control or Line Printer and clock calendar controls Serial Line 5 data I O or 8255 control 0 Seria...

Page 43: ...interrupt 13 routine Except for software interrupts there are only two timer interrupts available timers 0 and 2 can be used by the firmware 8255 PROGRAMMING Programming considerations for the 8255 P...

Page 44: ...DS 5 I DSR4 I DSR3 DSR2 DSRI lSBC 547 and lSBC 548 Boards 4 5 BAUD RATE PROGRAMMING ALL BOARDS To program the baud rate of a specific channel a time constant must be written to its time constant regi...

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Page 46: ...5 3 lists MULTIBUS connector P2 pin assignments Table 5 1 MULTIBUS Connector P1 Pin Assignments Component Side Circuit Side Pin Mneumonic Description Pin Mnemonic Description I GND Signal GND 2 GND S...

Page 47: ...DRC 46 ADRD 47 ADRA 48 ADRB 49 ADR8 ddress Bus 50 ADR9 Address Bus 51 ADR6 52 ADR7 53 ADR4 54 ADR5 55 ADR2 56 ADR3 57 ADRO 58 ADR1 59 DATE 60 DATF 61 DATC 62 DATD 63 DATA 64 DATB 65 DAT8 66 DAT9 67 DA...

Page 48: ...s the entire system to a known internal state The iSBC 546 iSBC 547 and iSBC 548 boards are slave boards and will never generate INIT These boards require an INIT pulse of 50 microseconds or longer fo...

Page 49: ...t a memory location address is on the MULTIBUS interface address lines and that the contents on the MULTIBUS interface data lines are to be written into that location XACK Transfer Acknowledge Indicat...

Page 50: ...20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 ADR16 Address 56 ADR17 Address 57 ADR14 Bus 58 ADR15 Bus 59 60 Note 1 If address lines AD...

Page 51: ...s the pin assignments for the iSBC 547 boards serial interface connectors and Table 5 6 shows the pin assignments for the iSBC 548 boards serial interface connectors Table 5 4 Serial Connectors Pin As...

Page 52: ...on1C 1nd1cates channel Table 5 5 serial Connectors Pin Assignments iSBC 547 Board Connector Jl Connector J2 Pin Mnemonic Description Mnemonic Description 1 CDl Carrier Detect 1 CD2 See 2 RXDl Receive...

Page 53: ...ic Deseription I1nemonic Description 1 CD5 See 1 CD6 See 2 RXD5 Description 2 RXD6 Description 3 TXD5 Connector Jl 3 TXD6 Connector Jl 4 DTR5 4 DTR6 5 GND 5 GND 6 DSR5 6 DSR6 7 RTS5 7 RTS6 8 CTS5 8 CT...

Page 54: ...ar to Send Ch7 5 14 TXD7 Transmit Data Ch7 2 15 RTS7 Reg to Send Ch7 4 16 RXD7 Receive Data Ch7 3 17 DSR7 Data Set Rdy Ch7 6 18 CD7 Carrier Detect Ch7 8 19 GND Ground 1 20 RI6 Ring indicator Ch6 22 21...

Page 55: ...ear to Send Ch3 5 14 TXD3 Transmit Data Ch3 2 15 RTS3 Req to Send Ch3 4 16 HXD3 Receive Data Ch3 3 17 DSR3 Data Set Rdy Ch3 6 18 CD3 Carrier Detect Ch3 8 19 GND Ground 1 20 RI2 Ring Indicator Ch2 22 2...

Page 56: ...be 2 LDATO Line Printer Data Bit 0 3 LDATI Line Printer Data Bit 1 4 LDAT2 Line Printer Data Bit 2 5 LDAT3 Line Printer Data Bit 3 6 LDAT4 Line Printer Data Bit 4 7 LDAT5 Line Printer Data Bit 5 8 LDA...

Page 57: ...into the line printer by LP STB Line Printer Acknowledge The line printer activates this signal to indicate it has accepted the data strobed off the data lines Line Printer Busy This signal is activa...

Page 58: ...on service areas Intel expects to ship 90 of these products within 48 hours of receiving the defective board The DRA service provides repair work Return the defective board to Intel freight prepaid an...

Page 59: ...02 869 4862 M 01H Figure 6 1 Territorial Service Telephone Numbers Before shipping remove all user modifications Protect the product from damage in transit as follows 1 Boards should be placed in anti...

Page 60: ...6 3 SERVICE DIAGRAMS Figure 6 2 is the schematic diagram for the iSBC 548 board Figure 6 3 is the schematic diagram for the iSBC 547 board and Figure 6 4 is the schematic diagram for the iSBC 546 boa...

Page 61: ...1 4U 5 r I 2 CAPAC1TOR VALUES ARE IH I1IeRO tARADS 3 NE ATIOH DENOTED BY AT THE END Of A SIGNAL NAME AT DAISY THIS IS TRANSL ATED TO rOR DOClIl1EHTATIOH PRIHTS 4 PRO RAMI ED DEli ICES AND JUI1PERS AR...

Page 62: ...SERVICE ASSISTANCE INFORMATION j II I I 1 a t I N I UI N il Q N l r g g l a e oJ I oI l 1 l a w IJ _ I t t t F f n _ z FO i i r _ _ Figure 6 2 iSBC 548 Schematic Diagram Sheet 2 of 11 6 5...

Page 63: ...r Ie I H e Il E 17 101 3 At 2 It IDE j I l I H I ICE le 10l 8 I 1011 AD 9 Af 8 1 PLI I ruc ALS c DENf I 18 I J lieu XACtc6EN I IAZ lY2 JADRF 741i1LS32 n A6INT LJ I II I H ACI IY4 UHe 1 2A Z YJ I II IO...

Page 64: ...TANCE INFORMATION Ii M a I r f M N JM J V tnVl Jl f J UUU UUUU _ l J Il 0 II Q CO H H 1f J_ U J Q U J I l Il l If if j C 0 U L Z Q I I l Q W 0 I 0 u Vl Q 5 Or ro _ Figure 6 2 iSBC 548 Schematic Diagra...

Page 65: ...SERVICE ASSISTANCE INFORMATION Ju I j I I Z I O II _ j Q o L_ A I j 9 l Figure 6 2 iSBC 548 Schematic Diagram Sheet 5 of 11 6 8...

Page 66: ...u ___ _ J t oJ _ u I I t if _ _____l I Ii OJ Ci Co woo _ J r D III _ _ _ _ _ w w f I R a u u Q III _ M JJ C J to 00 Ill 1 1 N N N ru ru I C J I _ N III a i Q Q Q a J J J J J J J _ l J J J J J J Figure...

Page 67: ...NFORMATION w J c f I 1 1 J l J F I 1 tL j t J __ L _ _ I t I 1 L I J 1 c j l I I i H 11 1 1 I I _ __ Me 0 J kL h _ _ _ r u ru ru y ru i I 0 J I t lCl IL J J l Qr l lLo Figure 6 2 iSBC 548 Schematic Di...

Page 68: ...SERVICE ASSISTANCE INFORMATION _ c l 1 I f o j In V II In ONM _ n J If j I Q I I I r I I I 1 _ i I_I _ I III Figure 6 2 iSBC 548 Schematic Diagram Sheet 8 of 11 6 11 1 i...

Page 69: ...SERVICE ASSISTANCE INFORMATION c e r V r HeN V r f II I 1 Figure 6 2 iSBC 548 Schematic Diagram Sheet 9 of 11 6 12 I...

Page 70: ...I I I SERVICE ASSISTANCE INFORMATION T I I I 112_ t t tJ nH I j t I I I 1 1 I I U I I l 1 1 I 1 i I i 1 i li j Jl I i i I I Figure 6 2 iSBC 548 Schematic Diagram Sheet 10 of 11 6 13...

Page 71: ...11 n l 1 ____ _ 4 4 11 1 1 1 1 1 1 1 _ _ II i I i I Ii II 1 1 1 1 I I I _ g ttt I 0 Q I lIInI A n I XI I Xt 0 1 1 l1li 1 111 111 NNN __ U llr o t lII 1 1 111 1 111 4 1 9E _ _ Figure 6 2 iSBC 548 Sche...

Page 72: ...3 U36 8 9 U 11 UI9 Uao U2 3 1486 I Ul6 U U U U2Z U5 U6 U9 i 1488 Ue U3 U4 U7 U8 1 1 0 1 1 RESISTOR VALUES ARE IN OHI IS 1 4 J 5 2 CAPACITOR VALUES ARE 11 1 nCRO rARADS 3 NE l ITlON DENOTED BY AT THE E...

Page 73: ...1 1 1 1 L Q I t U I A A 0 t v N Cl i tl N I o 1 1 1 1 1 1 1 1 J l I I I 1 11 1 1 1 1 1 A 1 1 1 00 1 1 Q ru M If 1 11 0 1 Q N If f 1 1 1 1 1 1 l I J aaa a 1 01 1 0 11 1 q m on MI I Z Q Q E Figure 6 3 i...

Page 74: ...SERVICE ASSISTANCE INFORMATION b 1 In l III n III D C I 0 a a 0 I t J Figure 6 3 iSBC 547 Schematic Diagram Sheet 3 of 12 6 17 l I i I...

Page 75: ...r ww z z SERVICE ASSISTANCE INFORMATION Figure 6 3 iSBC 547 Schematic Diagram Sheet 4 of 12 6 18...

Page 76: ...l SERVICE ASSISTANCE INFORMATION o f w w f f w w w Q Q J U U r I R l I 0 Ell _ t LV u I r R b b o Z U I 0 0 0 0 I _o uOI Io a _ U 1 1 I RRRR J _ N M UU Figure 6 3 iSBC 547 Schematic Diagram Sheet 5 of...

Page 77: ...tQ G t l a G 4 l l au U n l I I i lo lo l 1QI II IR G I J I I E P l In W a ct CI o lRl lo l dl t t I w 0 W 0 Q_ IM qq I l I a I I I Il U I b J I l l l iI 0 0 _ 10 _ _ ru y v In 4lI QJ tCI J rG tG Q l...

Page 78: ...SERVICE ASSISTANCE INFORMATION J D g tl I or Q to fJ nA 1 _ N jO N NN f N _ PI I I u j j a Co Cll tlQ CLG 0 16 0 u u L 0_ u Figure 6 3 iSBC 547 Schematic Diagram Sheet 7 of 12 6 21 9 N 0 uo u CJ UI CJ...

Page 79: ...DSR2 3 PlZ 12 17 1081 DSR3 A3 BJ 16 10Ie DSR4 5 Fl4 I OB3 DS 5 nSR DSR7 II DSRB llQ PCS r 19 i r l U 3 74ALS24 00 0 1 J g sJ n rt 12 13 US8 CLU 74AL S2 a U43 14LS73 of A2 2 16 fil3 5 IS 1114 AS 85 14...

Page 80: ...SERVICE ASSISTANCE INFORMATION H mr 8 ilTI ____ Figure 6 3 iSBC 547 Schematic Diagram Sheet 9 of 12 6 23...

Page 81: ...ANCE INFORMATION n m 0 n n x x x A I l ru N W II G 111111 UO RR W Ill l 1 _ __ j 1 n l A e A UU 0 M XA aua u u u u m JCUNru L _ _ _ _ _______________ _ __ _ Figure 6 3 iSBC 547 Schematic Diagram Sheet...

Page 82: ...SERVICE ASSISTANCE INFORMATION l o nc I ru x 0 _e xo u uo u uo C U 101 1 1 j ot r j l 9 b o _ _ ru l l r r r r J t k c L x e 0 0 01 0 Figure 6 3 iSBC 547 Schematic Diagram Sheet 11 of 12 6 25...

Page 83: ...SERVICE ASSISTANCE INFORMATION 0 l in t VI X Q 0 0 I l Il U DVlIII VlXIOI III U o l III U ll o N J _ r 9 m m I M 0_ 0_ 0_ _ 1 1 _ 11 l j Figure 6 3 iSBC 547 Schematic Diagram Sheet 12 of 12 6 26 w L N...

Page 84: ...ERVICE ASSISTANCE INFORMATION i i i U L N l e o t t t t t r t 1 t j 1 I r S I r T t t t I t t t t t t t 1 H t j D 0 Q If _ VI U Q U W II Figure 6 4 iSBC 546 Schematic Diagram Sheet 1 of 11 6 27 r I Q...

Page 85: ...ORMATION 0 Q I q III U R I 1 1 1 1 1 1 1 1 I I tctG RRAARAAA Q U YMN f1 ml MIIJ r Q IUM IO D 111111l1li111l1li111111 ll Q ruM Ifl ol l1li111111111 l1li 111 t I_CIIM I l ARARAARA Figure 6 4 iSBC 546 Sc...

Page 86: ...LS136 B PUF2 ALS04 PUP lIADRFI f ADR9 ADRii E15 111 ADR r AD ISl J ADR 9 3 ADRo ADlfs ADRC ADRD ADRE J cc o 32 II Iii 8 V m I rl lU I i p LN IA31Y3 ENI ACKIII IA4 Iy 2 74ASOC AlliS 18 8D 11 C L __ ll...

Page 87: ...xl Z 2 SERVICE ASSISTANCE INFORMATION w 0 t rJ ru 0 L M 0 Figure 6 4 iSBC 546 Schematic Diagram Sheet 4 of 11 6 30 x0 1 1 0 0 ruru I...

Page 88: ...SERVICE ASSISTANCE INFORMATION w t t l ill ill ill 0 o Figure 6 4 iSBC 546 Schematic Diagram Sheet 5 of 11 6 31...

Page 89: ...11 D D D dl SERVICE ASSISTANCE INFORMATION U 0_ o u u tl CU In J J OO J _ _ _ _ _ _ I I l I J l l I I I l J I J J J J J J_I J J J I J J t uu 0 c i1 1 __ 0 I 5 6 Figure 6 4 iSBC 546 Schematic Diagram S...

Page 90: ...r Ut4 UR D1 39 10B2 74ALS l 2 J 34 D221083 u I 8 DC DS 37 IOB6 LSD2 I I I I I peLI 1087 I I I ILA2 L Al U24 82530 108 7 1 I leeTSI 2 _ LIC CD Va 1489 UIO OB IHSI a l12 elK CK K OAr DB DC OD 1 ocl S D...

Page 91: ...I 1 I r r I 10 ru _ i L g r J g g l Mrlg g U I u L t U ru ru l f l J W c ITt 6 tl D 1 1 ru _ I _NO ruM I l m a t I r I a I t l NO l l IV M II D Vl J II 0 D Ill f I I Vl f D 0 D 1 Q J Z J Figure 6 4 i...

Page 92: ...SERVICE ASSISTANCE INFORMATION Figure 6 4 iSBC 546 Schematic Diagram Sheet 9 of 11 6 35...

Page 93: ...l I OJ 10 M J AlrbF f J1 ol ln r If C _ J In Lf t H I J I U 0 Pl XNu J a I Q 0 n J 1 00 f J M M M ru t l M M M M ru ru I J J J J J ULJUUU 0 0 t l _ ruM In J UOJOJ J M 11 1 qI lPlPlPlPlPlPl Lo o a CLo...

Page 94: ...SERVICE ASSISTANCE INFORMATION r _ O 0 R M O RM 0 R XR OUR OU OUR OU OUR OUR OU _ r L b L r r R r J It tt L L U i OR OR OR X X X X OR OR OR OR Figure 6 4 iSBC 546 Schematic Diagram Sheet 11 of 11 6 37...

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Page 96: ...lled by the factory sections A 3 through A 6 provide more detailed information about the jumpers Figures A I A 2 and A 3 show the location of the stake pins on each of the boards Table A l Jumper Defa...

Page 97: ...continued Functl on 546 Board Makes INT3 the MULTIBUS Interrupt when installed Makes INT4 the MULTIBUS Interrupt when when installed Dual Port RAM ddress Jumper installed to select mapping in the lowe...

Page 98: ...per Flag Byte Address Jumper Dual Port RAM Address Jumper Flag Byte Address Jumper Dual Port RAM Address Jumper Dual Port RAM Address Jumper 80186 Clockout Jumper Removed only during factory test Make...

Page 99: ...ed to select mapping in the upper MByte A 2 FLAG BYTE ADDRESS JUMPERS I O mapping of the flag byte is a jumper configurable option on the three controller boards Table A 3 shows the jumpers and config...

Page 100: ...24 Default installation iSBC 546 Selectable on all boards INT3 E27 E24 Default installation iSBC 547 and iSBC 548 Selectable on all boards INT4 E23 E24 Selectable on all boards INT5 E18 E21 Selectable...

Page 101: ...H X X X ODOOOO H X X ODSOOO H X X OEOOOO H X X OESOOO H X X OFOOOO H X OFSOOO H X FSOOOO H X X X FSSOOO H X X X F90000 H X X F9S000 H X X FAOOOO H X X FASOOO H X X FBOOOO H X FBSOOO H X FCOOOO H X X F...

Page 102: ...PER INFORMATION E15 0 o E17 P1 NOTES DEFAULT JUMPERS ARE E3 E4 E11 E12 E13 E14 E15 E17 E25 E24 E18 THROUGH E27 ARE LOCATED ON THE BOARD STAKE PINS ARE INSTALLED IN E19 E20 E24 E25 AND E27 ONLY COMPONE...

Page 103: ...8 E9 00 E12 E10 E13 E14 E18 E19 E20 E25 o 0 E26 E27 Figure A 2o JUMPER INFORMATION E15 0 o E17 iSBC NOTE DEFAULT JUMPERS ARE E3 E4 E7 E8 E9 E10 E13 E14 E15 E17 E24 E27 COMPONENT SIDE E28 00 E29 547 Bo...

Page 104: ...E12 E10 E13 E14 E18 E19 E20 E25 E26 E27 Figure A 3 P1 JUMPER INFORMATION E15 E17 COMPONENT SIDE NOTE DEFAULT JUMPERS ARE E3 E4 E7 E8 E9 E10 E13 E14 E15 E17 E24 E27 E28 E29 P2 iSBC 548 Board Jumper Loc...

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Page 106: ...547 548 firmware is released as a set of two Intel EPROMs The firmware makes the three boards into intelligent terminal controllers which can provide a MULTIBUS host CPU with either four iSBC 546 or...

Page 107: ...is transmitted The firmware provides software control of the Data Terminal Ready DTR line on all channels Transitions on the Carrier Detect CD line are sensed and reported to the host CPU Request to...

Page 108: ...ions to a line if an XOFF was received from this line and will resume only upon receipt of XON The firmware provides a capability to detect the baud rate of an agent connected to a serial channel The...

Page 109: ...oards are sharing the same I O address they all detect the same interrupt When the IN QUEUE is scanned the controllers that find no new commands ignore the interrupt and return to their states before...

Page 110: ...it s buffer immediately after receipt of the INPUT AVAILABLE message By not clearing the buffer immediately the number of interrupts from the controller board will be reduced Both host and controller...

Page 111: ...the controllers follows in section B 3 2 Section B 3 3 details the implementation of the message passing scheme section B 3 4 details the power up confidence tests B 3 l STRUCTURES OF DUAL PORTED RAM...

Page 112: ...xecutes a far jump to the address specified by a 32 bit 8086 style pointer 16 bit offset plus 16 bit selector in the next four bytes If the pattern is not loaded within the 250 ms the firmware continu...

Page 113: ...iSBC 548 board To use an iSBC 188 48 driver with this firmware requires that it be modified to recognize the new board types iSBC 546 547 548 version This value indicates the version of the firmware...

Page 114: ...FIRMWARE Size Offset 124 1 1 1 1 Reserved Confidence Test Result Completion Flag Version Board Type 20 19 18 17 16 NOTE Reserved space should be set to 00 H Figure B 3 static structure Area Layout B 9...

Page 115: ...layout of the Dynamic structures area the semantics are described in section B 3 3 B 3 1 4 Size 124 1 1 1 1 Reserved OUT Queue OUT Queue IN Queue IN Queue Figure B 4 Queue Head Tail Head Tail Offset 1...

Page 116: ...age formats and protocol used for communication between the host CPU and the controllers section B 3 2 1 describes the messages sent by the host CPU to the controllers section B 3 2 2 describes the me...

Page 117: ...ine command before it can be used The only line specific commands that can be directed to a disabled line are Configure Line and Enable Line The controllers return an Initialize Complete message conta...

Page 118: ...odem control signals are asserted and cleared respectively An Enable Line command received when the line is already enabled is ignored by the controllers An Enable Command to the line printer causes a...

Page 119: ...the line is quiescent as it clears the state f the channel with any pending output being cancelled and any received characters discarded Further if a pending transmit operation is cancelled in this pr...

Page 120: ...ing transmit operation is cancelled in this process no Transmit Complete message is returned This command is accepted when the line is disabled The Configure message format is shown in Figure B 9 Mess...

Page 121: ...omatic baud rate recognition mode In this mode the controller attempts to sense the baud rate of an agent connected to the serial channel The remote agent is required to transmit a maximum of four ASC...

Page 122: ...OH This block is assigned for future firmware imple mentations which support more complex functions This block is set to OIH for this application Used to set special modes Bit 0 Bit 1 Bit 2 Tandem Mod...

Page 123: ...e controller Consequently the host does not see the interrupt character until all the data characters preceding it have been copied out of the controller The Signal on Character mode provides a soluti...

Page 124: ...et in the Signal on Special Character mode Line parameters are set to the following defaults on reset 9600 baud 7 bits character 1 stop bit Even parity Tandem mode OFF Signal on special Character mode...

Page 125: ...ost A transmit command is ignored if the line is transmitting a break or has not been enabled or has been placed in an automatic baud rate recognition mode by a previously issued configure command A t...

Page 126: ...ty at the beginning of the transmit buffer in the dual ported address space of the controllers The host CPU fills the transmit buffer by writing into it directly prior to issuing this command In the 6...

Page 127: ...the command is ignored otherwise a Transmit Complete message is returned If there are multiple outstanding transmit requests for the line only the current the one issued the earliest is aborted Figure...

Page 128: ...nored A suspended transmission can be resumed with a subsequent Resume Transmit command If there are multiple outstanding transmit requests for the line the line will remain suspended until a Resume T...

Page 129: ...in progress on the line or if the transmission is not suspended the command is ignored Figure B 13 shows the Resume Transmit message format Message Format a 1 2 08H Line Number Reserved NOTE Reserved...

Page 130: ...Detect signal Thus the MULTIBUS host can maintain a state variable following the Carrier Detect modem signal by toggling the variable when subsequent Carrier Detect and Carrier Loss messages are rece...

Page 131: ...t to transmit unless CTS is active and not to receive unless CD is active Figure B 15 shows the command format Message Format NOTE 0 OAH Reserved space should be set to 1 Line Number 00 H 2 Reserved 1...

Page 132: ...specified line regardless of CTS and CD This is the default condition after reset Figure B 16 shows the command format Message Format NOTE 0 OBH Reserved space should be set to 1 Line Number 00 H 2 Re...

Page 133: ...lers to report changes of the DSR signal on the specified line Figure B 17 shows the command format Message Format o OCH 1 Line Number 2 Reserved 15 Reserve NOTE Reserved space should be set to 00 H L...

Page 134: ...DSR changes on the specified line This is the default condition after reset Figure B 18 shows the command format Message Format a 1 2 15 Line Number NOTE aDH Reserved space should be set to Line Numb...

Page 135: ...lers to report changes of the RI signal on the specified line Figure B 19 shows the command format Message Format 0 1 2 15 Line Number NOTE OEH Reserved space should be set to Line Number 00 H Reserve...

Page 136: ...request to report RI changes for the specified line Figure Figure B 20 shows the command format Message Format 0 1 2 15 Line Number NOTE OFH Reserved space should be set to Line Number 00 H Reserved...

Page 137: ...erminal ready modem signal on a serial channel Figure B 2l shows the Clear DTR message format Message Format o lOH 1 Line Number 2 Reserved 15 I Reserved NOTE Reserved space should bE set to 00 H Line...

Page 138: ...on is in progress on the line Once a set Break command is issued it must be followed by a Clear Break command before any transmit Buffer commands are issued on the particular line Figure B 22 shows th...

Page 139: ...tion on a line caused by a previous Send Break command Figure B 23 shows the Clear Break message format Message Format o 1 2 l2H Line Number Reserved NOTE Reserved space should be set to 00 H 15 I Res...

Page 140: ...FIRMWARE This page intentionally left blank...

Page 141: ...the MULTIBUS host since the Download command and subsequent Execute command use the normal message interface care must be taken not to overwrite memory used to implement the queues or the lower 16K o...

Page 142: ...ontroller where the code is to be loaded Source Offset The l6 bit offset in the controllers dual ported RAM from where the controller is to copy the code to the destination address plus 16384 The code...

Page 143: ...B 25 shows the Execute command message format Message Format start Address Response o l4H 1 Reserved 2 start Addr Offset 3 4 l tart Addr Selector 5 6 Reserved 15 1 1_ _ _ _ R_e_s_e_r_ _ _e_d___ NOTE R...

Page 144: ...important synchronization function The controllers ensure that at most one Input Available message per line is pending That is it issues an Input Available message on a particular line only after any...

Page 145: ...h characters have been cleared The number of characters copied out of the receive buffer The count can be O The count must not exceed the count specified in the corresponding Input Available message N...

Page 146: ...to request another Transmit Buffer operation Table B 27 shows the Transmit Complete message format Message Format Line Number Actual Count Response o OlH 1 Line Number 2 Actual Count 3 4 Reserved 151...

Page 147: ...ot issue any further Input Available messages for the channel until the host CPU responds with a Clear Receive Buffer message Thus some measure of flow control can be exercised by the host CPU Note th...

Page 148: ...y to the beginning of the area where the received characters have been accumulated The firmware adds 16384 bytes to maintain compatibility with other Intel products The number of characters available...

Page 149: ...letion of a previously issued Download command This message also clears the host CPU to issue another Download command or an Execute command Figure B 29 shows the Download Complete message format Mess...

Page 150: ...ugh an OFF to ON transition was not sensed on the Carrier Detect signal Thus the host can maintain a state variable following the Carrier detect modem signal by toggling the variable when subsequent C...

Page 151: ...ition is detected on the Carrier Detect Modem line Figure B 31 shows the Carrier Loss message format Message Format Line Number Hesponse o 05H 1 Line Number 2 Reserved 1511 ____R_e_s_e_r_v_e_d___ I NO...

Page 152: ...ubsequent line specific commands Figure B 32 shows the Initialization Responses message format Message Format Active Lines o 1 2 3 4 15 06H Reserved Active Lines Reserved Reserved Reserved NOTE Reserv...

Page 153: ...to issue line specific commands to the line after it receives this message Figure B 33 shows the Autobaud Complete message format Message Format Line Number Baud Rate Response o 07H 1 Line Number 2 Ba...

Page 154: ...of the line exceeds the Signal Special Character high water mark Figure 5 34 shows the Special Character Received message Message Format o OSH 1 Line Number 2 Special Character 3 Reserved 15 I Reserve...

Page 155: ...reports DSR going active on the specified line The line is in DSR Report Mode Message Format 0 1 2 15 Line Number NOTE 09H Reserved space should be set to Line Number 00 H Reserved Reserved The serial...

Page 156: ...eports DSR going inactive on the specified line The line is in DSR Report Mode Message Format 0 1 2 15 Line Number NOTE OAH Reserved space should be set to Line Number 00 H Reserved Reserved The seria...

Page 157: ...CT This message reports RI going active on the specified line Message Format NOTE 0 OBH Reserved space should be set to 1 Line Number 00 H 2 Reserved 15 Reserved Line Number The serial channel on whic...

Page 158: ...T This message reports RI going inactive on the specified line Message Format 0 1 2 15 Line Number NOTE OCH Reserved space should be set to Line Number 00 H Reserved Reserved The serial channel on whi...

Page 159: ...mal operation on a single line HOST CPU CONTROLLERS RESET 1 INITIALIZE 2 INITIALIZATION RESPONSE 3 CONFIGURE 4 ENABLE LINE 5 ASSERT DTR Modern establishes carrier 6 CARRIER DETECT Host copies data int...

Page 160: ...only input possible from this line is a byte of printer status the line printer corresponds to iSBC 546 line 5 Channel 4 when counting from 0 to 7 To read the status of the line printer a Clear Receiv...

Page 161: ...t and receive Buffers to set and read the time To set the time a Transmit command is issued with 11 bytes of data in the Transmit Buffer To read the time a Clear Receive Buffer command is issued with...

Page 162: ...the OUT queue area refers to the corresponding array used for messages from the controller To be definitive consider the following array declarations made for the two queue areas and the control varia...

Page 163: ...e controller In the following procedures the host CPU is allowed to modify In_Clueue_tail and Out_queue_head but is allowed only to read In_queue_head and out_queue_tail Send Message wait until In que...

Page 164: ...ctions Table B 2 Confidence Test Result Codes Result Test 00 EPROM Checksum Test 10 DRAM March Test 11 DRAM Ripple Test 30 PIT Countdown Test 50 SCC Register Test 51 SCC Register Test 52 SCC Register...

Page 165: ...PROM size is never more than 64 KBytes Figure B 29 shows the format of the Checksum Test Note that the checksum is defined not to include the sum of the EPROM addresses in which the checksum itself is...

Page 166: ...The procedure is repeated for all of the on board non dual ported RAM for RAM address 0 to 17FFEH do for each Pattern do write Pattern to RAM address read Check Pattern from RAM addressi if Check Pat...

Page 167: ...nt time Max Count Register A as 0064H loop up to 100 times read PIC POLL Register if most significant bit is ON and highest_level 0 then pass test end if end loop fail test B 3 4 4 sec Register Test T...

Page 168: ...wing procedure is used set timer to interrupt every 1 5 msec On the first interrupt read and store time On the second interrupt set time to 12 31 7 23 59 99 90 On the third interrupt read the time it...

Page 169: ......

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