2.3.2. Clocking Scheme
Figure 16.
Parallel Loopback with Simplex Mode
F-tile PMA/
FEC Direct
PHY IP (TX)
SDI II
(TX)
TX PLL Refclock
System PLL Refclock
RX Coreclock/DR Clocks
RX CDR Refclock
TX PLL/RX CDR Link Clock
System PLL Output Link Clock
TX/RX Transceiver Clkout
TX/RX Transceiver Clkout2
Top
Rx Top
TX Top
Loopback
FIFO
SDI RX Sys
Loopback Top
SDI TX Sys
SDI F-tile
PHY Adapter
F-tile PMA/
FEC Direct
PHY IP (RX)
SDI II
(RX)
SDI F-tile
PHY Adapter
Device_init
GPIO Clock
TX PLL
Ref Clock
SysPLL
Ref Clock
RX CDR
Ref Clock
Reference
and System
PLL Clocks IP
2. Design Example Detailed Description
710496 | 2022.01.28
F-Tile SDI II Intel
®
Agilex
™
FPGA IP Design Example User Guide
22
