Intel Core i7 Extreme Edition Datasheet Download | Manualshive

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Features

92

Datasheet

If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and

for processors with an integrated memory controller, the DRAM will be put into self-

refresh.

7.2.2.4

Package C6 State

The package will enter the C6 low power state when all cores are in the C6 or lower

power state and the processor has been granted permission by the other component(s)

in the system to enter the C6 state. The package will also enter the C6 state when all

cores are in an idle state lower than C6 but the other component(s) have only granted

permission to enter C6.

If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and

the shared cache will enter a deep sleep state. Additionally, for processors with an

integrated memory controller, the DRAM will be put into self-refresh.

7.3

Sleep States

The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in. For

information on ACPI S-states and related terminology, refer to ACPI Specification. The

S-state transitions are coordinated by the processor in response PM Request (PMReq)

messages from the chipset. The processor itself will never request a particular S-state.

Notes:

1.

If the chipset requests an S-state transition which is not allowed, a machine check error
will be generated by the processor.

7.4

ACPI P-States (Intel

®

Turbo Boost Technology)

The processor supports ACPI P-States. A new feature is that the P0 ACPI state will be a
request for Intel Turbo Boost Technology. This technology opportunistically and
automatically allows the processor to run faster than its marked frequency if the
processor is operating below power, thermal, and current specifications. Maximum
turbo frequency is dependant on the processor component and number of active cores.
No special hardware support is necessary for Intel Turbo Boost Technology. BIOS and
the operating system can enable or disable Intel Turbo Boost Technology.

Table 7-3.

Processor S-States

S-State

Power Reduction

Allowed Transitions

S0

Normal Code Execution

S1 (via PMReq)

S1

Cores in C1E like state, processor responds with
CmpD(S1) message.

S0 (via reset or PMReq)
S3, S4 (via PMReq)

S3

Memory put into self-refresh, processor responds
with CmpD(S3) message.

S0 (via reset)

S4/S5

Processor responds with CmpD(S4/S5) message.

S0 (via reset)

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Summary of Contents for Core i7 Extreme Edition

Page 1: ...Document 320834 001 Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor Datasheet Volume 1 November 2008...

Page 2: ...and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel c...

Page 3: ...shoot Specification 29 2 11 3 Die Voltage Validation 30 3 Package Mechanical Specifications 31 3 1 Package Mechanical Drawing 31 3 2 Processor Component Keep Out Zones 34 3 3 Package Loading Specifica...

Page 4: ...d Lines 25 2 4 VTT Static and Transient Tolerance Load Line 27 2 5 VCC Overshoot Example Waveform 30 3 1 Processor Package Assembly Sketch 31 3 2 Processor Package Drawing Sheet 1 of 2 32 3 3 Processo...

Page 5: ...Group DC Specifications 28 2 15 Control Sideband Signal Group DC Specifications 29 2 16 VCC Overshoot Specifications 29 3 1 Processor Loading Specifications 34 3 2 Package Handling Guidelines 34 3 3...

Page 6: ...6 Datasheet...

Page 7: ...anced video audio encryption and 3D performance New accelerators for improved string and text processing operations Power Management capabilities System Management mode Multiple low power states 8 way...

Page 8: ...8 Datasheet Revision History Revision Number Description Date 001 Initial release November 2008...

Page 9: ...tel Core i7 processors i7 940 and i7 920 Note The Intel Core i7 processor Extreme Edition refers to the Intel Core i7 processor Extreme Edition i7 965 The processor is optimized for performance with t...

Page 10: ...le Data Rate 3 Synchronous Dynamic Random Access Memory SDRAM is the name of the new DDR memory standard that is being developed as the successor to DDR2 SRDRAM Intel QuickPath Interconnect Intel QPI...

Page 11: ...te The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any su...

Page 12: ...Introduction 12 Datasheet...

Page 13: ...VCC 8 VTTA pads and 5 VSS pads associated with VTTA 28 VTTD pads and 17 VSS pads associated with VTTD 28 VDDQ pads and 17 VSS pads associated with VDDQ and 3 VCCPLL pads All VCCP VTTA VTTD VDDQ and V...

Page 14: ...o core frequency is configured during power on reset by using values stored internally during manufacturing The stored value sets the highest core multiplier at which the particular processor can oper...

Page 15: ...VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1 04375 0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1 03750 0 0 0 0 0 0 1 0 1 60000 0 1 0 1 1 1 0 1 1 03125 0 0 0 0 0 0 1 1 1 59375 0 1 0 1...

Page 16: ...0 1 27500 1 0 0 1 0 0 0 1 0 70625 0 0 1 1 0 1 1 1 1 26875 1 0 0 1 0 0 1 0 0 70000 0 0 1 1 1 0 0 0 1 26250 1 0 0 1 0 0 1 1 0 69375 0 0 1 1 1 0 0 1 1 25625 1 0 0 1 0 1 0 0 0 68750 0 0 1 1 1 0 1 0 1 250...

Page 17: ...esistor will also allow for system testability 0 1 0 0 1 1 1 1 1 11875 1 0 1 0 1 0 1 0 0 55000 0 1 0 1 0 0 0 0 1 11250 1 0 1 0 1 0 1 1 0 54375 0 1 0 1 0 0 0 1 1 10625 1 0 1 0 1 1 0 0 0 53750 0 1 0 1 0...

Page 18: ...eference Clocks Differential DDR3 Output DDR 0 1 2 _CLK D P 3 0 DDR3 Command Signals Single ended CMOS Output DDR 0 1 2 _RAS DDR 0 1 2 _CAS DDR 0 1 2 _WE DDR 0 1 2 _MA 15 0 DDR 0 1 2 _BA 2 0 Single en...

Page 19: ...onnection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor be first in the TAP chain and followed by any other components...

Page 20: ...fications shown in Table 2 5 is used with devices normally operating from a VTTD interface supply VTTD nominal levels will vary between processor families All PECI devices will operate at the VTTD lev...

Page 21: ...ected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding t...

Page 22: ...band and Test Access Port TAP are listed in Table 2 12 through Table 2 15 Table 2 7 through Table 2 15 list the DC specifications for the processor and are valid only while meeting specifications for...

Page 23: ...n 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Refer to Table 2 8 and Figure 2 3 for the minimum typical and maximum VCC allowed for a given current The proc...

Page 24: ...ID 0 020 VID 0 039 VID 0 058 1 2 3 30 VID 0 024 VID 0 043 VID 0 062 1 2 3 35 VID 0 028 VID 0 047 VID 0 066 1 2 3 40 VID 0 032 VID 0 051 VID 0 070 1 2 3 45 VID 0 036 VID 0 055 VID 0 074 1 2 3 50 VID 0...

Page 25: ...5 VID4 VID3 VID2 VID1 VID0 0 1 0 0 0 0 1 0 1 220 V 0 1 0 0 0 1 1 0 1 195 V 0 1 0 0 1 0 1 0 1 170 V 0 1 0 0 1 1 1 0 1 145 V 0 1 0 1 0 0 1 0 1 120 V 0 1 0 1 0 1 1 0 1 095 V 0 1 0 1 1 0 1 0 1 070 V 0 1 0...

Page 26: ...VID 0 0045 VID 0 0360 VID 0 0675 7 VID 0 0105 VID 0 0420 VID 0 0735 8 VID 0 0165 VID 0 0480 VID 0 0795 9 VID 0 0225 VID 0 0540 VID 0 0855 10 VID 0 0285 VID 0 0600 VID 0 0915 11 VID 0 0345 VID 0 0660...

Page 27: ...ut High Voltage 0 57 VDDQ V 3 VOL Output Low Voltage VDDQ 2 RON RON RVTT_TERM V VOH Output High Voltage VDDQ VDDQ 2 RON RON RVTT_TERM V 4 RON DDR3 Clock Buffer On Resistance 21 31 RON DDR3 Command Buf...

Page 28: ...frequencies 2 The VTTA referred to in these specifications refers to instantaneous VTTA 3 For Vin between 0 V and VTTA Measured when the driver is tristated 4 VIH and VOH may experience excursions ab...

Page 29: ...rom a high to low current load condition This overshoot cannot exceed VID VOS_MAX VOS_MAX is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measur...

Page 30: ...ed across the VCC_SENSE and VSS_SENSE lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limi...

Page 31: ...hermal Interface Material TIM Processor core die Package substrate Capacitors Note 1 Socket and motherboard are included for reference and are not part of processor package 3 1 Package Mechanical Draw...

Page 32: ...Package Mechanical Specifications 32 Datasheet Figure 3 2 Processor Package Drawing Sheet 1 of 2...

Page 33: ...Datasheet 33 Package Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 2...

Page 34: ...g in a direction normal to the processor IHS 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface...

Page 35: ...ackage components and associated materials 3 8 Processor Markings Figure 3 4 shows the topside markings on the processor This diagram is to aid in the identification of the processor Table 3 3 Process...

Page 36: ...t 3 9 Processor Land Coordinates Figure 3 5 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Processo...

Page 37: ...KE 0 C29 CMOS O DDR0_CKE 1 A30 CMOS O DDR0_CKE 2 B30 CMOS O DDR0_CKE 3 B31 CMOS O DDR0_CLK_N 0 K19 CLOCK O DDR0_CLK_N 1 C19 CLOCK O DDR0_CLK_N 2 E18 CLOCK O DDR0_CLK_N 3 E19 CLOCK O DDR0_CLK_P 0 J19 C...

Page 38: ...DR0_DQ 7 T42 CMOS I O Table 4 1 Land Listing by Land Name Sheet 3 of 36 Land Name Land No Buffer Type Direction DDR0_DQ 8 N41 CMOS I O DDR0_DQ 9 N43 CMOS I O DDR0_DQS_N 0 U43 CMOS I O DDR0_DQS_N 1 M41...

Page 39: ...DQ 23 H36 CMOS I O Table 4 1 Land Listing by Land Name Sheet 5 of 36 Land Name Land No Buffer Type Direction DDR1_DQ 24 H33 CMOS I O DDR1_DQ 25 L33 CMOS I O DDR1_DQ 26 K32 CMOS I O DDR1_DQ 27 J32 CMOS...

Page 40: ..._MA 7 D22 CMOS O DDR1_MA 8 E22 CMOS O Table 4 1 Land Listing by Land Name Sheet 7 of 36 Land Name Land No Buffer Type Direction DDR1_MA 9 G24 CMOS O DDR1_ODT 0 D11 CMOS O DDR1_ODT 1 C8 CMOS O DDR1_ODT...

Page 41: ...2_DQ 53 N7 CMOS I O Table 4 1 Land Listing by Land Name Sheet 9 of 36 Land Name Land No Buffer Type Direction DDR2_DQ 54 R10 CMOS I O DDR2_DQ 55 R9 CMOS I O DDR2_DQ 56 U5 CMOS I O DDR2_DQ 57 U6 CMOS I...

Page 42: ...d Name Sheet 11 of 36 Land Name Land No Buffer Type Direction QPI_DRX_DN 3 AY36 QPI I QPI_DRX_DN 4 BA37 QPI I QPI_DRX_DN 5 AW38 QPI I QPI_DRX_DN 6 AY38 QPI I QPI_DRX_DN 7 AT39 QPI I QPI_DRX_DN 8 AV40...

Page 43: ..._DP 4 AH40 QPI O QPI_DTX_DP 5 AK40 QPI O QPI_DTX_DP 6 AH41 QPI O QPI_DTX_DP 7 AK42 QPI O QPI_DTX_DP 8 AJ43 QPI O QPI_DTX_DP 9 AG40 QPI O RESET AL39 Asynch I RSVD D35 RSVD D34 RSVD C36 RSVD A36 RSVD F3...

Page 44: ...17 RSVD J15 RSVD T40 Table 4 1 Land Listing by Land Name Sheet 15 of 36 Land Name Land No Buffer Type Direction RSVD L38 RSVD G38 RSVD J11 RSVD K8 RSVD P4 RSVD V7 RSVD G31 RSVD T35 RSVD U40 RSVD M38 R...

Page 45: ...8 RSVD AL4 RSVD AL40 Table 4 1 Land Listing by Land Name Sheet 17 of 36 Land Name Land No Buffer Type Direction RSVD AL41 RSVD AL5 RSVD AL6 RSVD AL8 RSVD AM1 RSVD AM2 RSVD AM3 RSVD AM36 RSVD AM38 RSVD...

Page 46: ...me Sheet 19 of 36 Land Name Land No Buffer Type Direction RSVD F27 RSVD F28 RSVD G28 RSVD H29 RSVD J29 RSVD K15 RSVD K24 RSVD K25 RSVD K27 RSVD K29 RSVD L15 RSVD U11 RSVD V11 RSVD AK7 SKTOCC AG36 GTL...

Page 47: ...AN21 PWR VCC AN24 PWR Table 4 1 Land Listing by Land Name Sheet 21 of 36 Land Name Land No Buffer Type Direction VCC AN25 PWR VCC AN27 PWR VCC AN28 PWR VCC AN30 PWR VCC AN31 PWR VCC AN33 PWR VCC AN34...

Page 48: ...AV16 PWR VCC AV18 PWR Table 4 1 Land Listing by Land Name Sheet 23 of 36 Land Name Land No Buffer Type Direction VCC AV19 PWR VCC AV21 PWR VCC AV24 PWR VCC AV25 PWR VCC AV27 PWR VCC AV28 PWR VCC AV30...

Page 49: ...V33 PWR Table 4 1 Land Listing by Land Name Sheet 25 of 36 Land Name Land No Buffer Type Direction VCCPLL W33 PWR VCCPWRGOOD AR7 Asynch I VDDPWRGOOD AA6 Asynch I VDDQ A14 PWR VDDQ A19 PWR VDDQ A24 PWR...

Page 50: ...VSS AC5 GND VSS AC7 GND VSS AC9 GND VSS AD11 GND VSS AD33 GND Table 4 1 Land Listing by Land Name Sheet 27 of 36 Land Name Land No Buffer Type Direction VSS AD37 GND VSS AD41 GND VSS AD43 GND VSS AE2...

Page 51: ...S AN3 GND VSS AN32 GND Table 4 1 Land Listing by Land Name Sheet 29 of 36 Land Name Land No Buffer Type Direction VSS AN35 GND VSS AN37 GND VSS AN41 GND VSS AN7 GND VSS AP1 GND VSS AP10 GND VSS AP11 G...

Page 52: ...VSS AW14 GND VSS AW17 GND Table 4 1 Land Listing by Land Name Sheet 31 of 36 Land Name Land No Buffer Type Direction VSS AW20 GND VSS AW22 GND VSS AW23 GND VSS AW26 GND VSS AW29 GND VSS AW32 GND VSS...

Page 53: ...S L29 GND VSS L34 GND Table 4 1 Land Listing by Land Name Sheet 33 of 36 Land Name Land No Buffer Type Direction VSS L39 GND VSS L4 GND VSS L9 GND VSS M12 GND VSS M14 GND VSS M16 GND VSS M18 GND VSS M...

Page 54: ...A AF33 PWR VTTA AF34 PWR VTTA AG34 PWR VTTD AA10 PWR VTTD AA11 PWR VTTD AA33 PWR VTTD AB10 PWR VTTD AB11 PWR VTTD AB33 PWR VTTD AB34 PWR VTTD AB8 PWR VTTD AB9 PWR VTTD AC10 PWR Table 4 1 Land Listing...

Page 55: ...SS GND AA33 VTTD PWR AA34 VSS GND AA35 DDR1_DQ 4 CMOS I O AA36 DDR1_DQ 1 CMOS I O AA37 DDR1_DQ 0 CMOS I O AA38 VSS GND AA39 VSS GND AA4 BCLK_ITP_DN CMOS O AA40 RSVD AA41 RSVD AA5 BCLK_ITP_DP CMOS O AA...

Page 56: ...VSS GND Table 4 2 Land Listing by Land Number Sheet 3 of 36 Land No Pin Name Buffer Type Direction AE3 RSVD AE33 VTTA PWR AE34 VTTD PWR AE35 VTTD PWR AE36 VTT_SENSE Analog AE37 VSS_SENSE_VTT Analog AE...

Page 57: ...QPI O AH41 QPI_DTX_DP 6 QPI O AH42 QPI_DTX_DN 6 QPI O Table 4 2 Land Listing by Land Number Sheet 5 of 36 Land No Pin Name Buffer Type Direction AH43 QPI_DTX_DN 8 QPI O AH5 FC_AH5 AH6 RSVD AH7 VSS GN...

Page 58: ...WR AL13 VCC PWR AL14 VSS GND AL15 VCC PWR Table 4 2 Land Listing by Land Number Sheet 7 of 36 Land No Pin Name Buffer Type Direction AL16 VCC PWR AL17 VSS GND AL18 VCC PWR AL19 VCC PWR AL2 VSS GND AL2...

Page 59: ...AM8 RSVD Table 4 2 Land Listing by Land Number Sheet 9 of 36 Land No Pin Name Buffer Type Direction AM9 VSS GND AN1 RSVD AN10 VID 4 CSC 1 CMOS I O AN11 VSS GND AN12 VCC PWR AN13 VCC PWR AN14 VSS GND...

Page 60: ...AP4 RSVD Table 4 2 Land Listing by Land Number Sheet 11 of 36 Land No Pin Name Buffer Type Direction AP40 QPI_DRX_DN 17 QPI I AP41 QPI_DRX_DP 17 QPI I AP42 QPI_DRX_DP 13 QPI I AP43 VSS GND AP5 VSS GND...

Page 61: ...CC PWR AT31 VCC PWR AT32 VSS GND Table 4 2 Land Listing by Land Number Sheet 13 of 36 Land No Pin Name Buffer Type Direction AT33 VCC PWR AT34 VCC PWR AT35 VSS GND AT36 RSVD AT37 QPI_DRX_DP 0 QPI I AT...

Page 62: ...V24 VCC PWR AV25 VCC PWR Table 4 2 Land Listing by Land Number Sheet 15 of 36 Land No Pin Name Buffer Type Direction AV26 VSS GND AV27 VCC PWR AV28 VCC PWR AV29 VSS GND AV3 VTT_VID2 CMOS O AV30 VCC PW...

Page 63: ...AY2 VSS GND Table 4 2 Land Listing by Land Number Sheet 17 of 36 Land No Pin Name Buffer Type Direction AY20 VSS GND AY21 VCC PWR AY22 VSS GND AY23 VSS GND AY24 VCC PWR AY25 VCC PWR AY26 VSS GND AY27...

Page 64: ...PWR BA14 VSS GND BA15 VCC PWR BA16 VCC PWR Table 4 2 Land Listing by Land Number Sheet 19 of 36 Land No Pin Name Buffer Type Direction BA17 VSS GND BA18 VCC PWR BA19 VCC PWR BA20 VSS GND BA24 VCC PWR...

Page 65: ...VDDQ PWR D19 DDR0_CLK_P 1 CLOCK O D2 BPM 6 GTL I O Table 4 2 Land Listing by Land Number Sheet 21 of 36 Land No Pin Name Buffer Type Direction D20 RSVD D21 DDR1_CLK_N 0 CLOCK O D22 DDR1_MA 7 CMOS O D2...

Page 66: ...34 CMOS I O F10 DDR1_DQ 36 CMOS I O F11 DDR1_ODT 3 CMOS O F12 DDR0_ODT 0 CMOS O Table 4 2 Land Listing by Land Number Sheet 23 of 36 Land No Pin Name Buffer Type Direction F13 DDR2_ODT 1 CMOS O F14 VD...

Page 67: ...nd Listing by Land Number Sheet 25 of 36 Land No Pin Name Buffer Type Direction G6 DDR1_DQS_N 5 CMOS I O G7 VSS GND G8 DDR1_DQ 37 CMOS I O G9 DDR1_DQ 44 CMOS I O H1 DDR0_DQ 41 CMOS I O H10 VSS GND H11...

Page 68: ...CMOS I O Table 4 2 Land Listing by Land Number Sheet 27 of 36 Land No Pin Name Buffer Type Direction J38 VSS GND J39 DDR2_DQ 19 CMOS I O J4 DDR1_DQ 52 CMOS I O J40 DDR2_DQ 18 CMOS I O J41 DDR0_DQ 21 C...

Page 69: ...3 CMOS O L28 DDR1_MA 3 CMOS O L29 VSS GND L3 DDR0_DQ 46 CMOS I O Table 4 2 Land Listing by Land Number Sheet 29 of 36 Land No Pin Name Buffer Type Direction L30 DDR1_DQS_P 3 CMOS I O L31 DDR1_DQS_N 3...

Page 70: ...I O Table 4 2 Land Listing by Land Number Sheet 31 of 36 Land No Pin Name Buffer Type Direction N42 RSVD N43 DDR0_DQ 9 CMOS I O N5 VSS GND N6 DDR2_DQ 49 CMOS I O N7 DDR2_DQ 53 CMOS I O N8 DDR2_DQ 52...

Page 71: ...U10 DDR2_DQ 59 CMOS I O U11 RSVD U2 VSS GND U3 DDR0_DQ 61 CMOS I O Table 4 2 Land Listing by Land Number Sheet 33 of 36 Land No Pin Name Buffer Type Direction U33 VCCPLL PWR U34 DDR2_DQ 4 CMOS I O U3...

Page 72: ...I O W7 DDR1_DQ 57 CMOS I O W8 VSS GND W9 DDR1_DQ 63 CMOS I O Table 4 2 Land Listing by Land Number Sheet 35 of 36 Land No Pin Name Buffer Type Direction Y1 VSS GND Y10 DDR1_DQ 58 CMOS I O Y11 VSS GND...

Page 73: ...I_DRX_DP 19 0 I I QPI_DRX_DN 19 0 and QPI_DRX_DP 19 0 comprise the differential receive data for the QPI port The inbound 20 lanes are connected to another component s outbound direction QPI_DTX_DN 19...

Page 74: ...indication that the VR controller does not currently need to be able to provide ICC above 20A and the VR controller can use this information to move to more efficient operation point This signal will...

Page 75: ...ore a subsequent rising edge of VCCPWRGOOD In addition at the time VCCPWRGOOD is asserted RESET must be active The PWRGOOD signal must be supplied to the processor It should be driven high throughout...

Page 76: ...is input signal to be a clean indication that the VTT power supply is stable and within specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches...

Page 77: ...o the processor case temperature thermal profile at the customer defined boundary conditions is expected to be compliant with this update No redesign of the thermal solution should be necessary A fan...

Page 78: ...appropriate processor Thermal and Mechanical Design Guide see Section 1 2 for details on system thermal solution design thermal profiles and environmental considerations Notes 1 These values are speci...

Page 79: ...in C y 43 2 0 19 P Table 6 2 Processor Thermal Profile Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C 0 43 2 34 49 7 68 56 1 100 62 2 2 43 6 36 50 0 70 56 5 102 62 6...

Page 80: ...ines see Section 1 2 for details on characterizing the fan speed to CA and ambient temperature measurement Notes 1 The ambient temperature is measured at the inlet to the processor thermal solution 2...

Page 81: ...hodology and attaching the thermocouple refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Notes 1 Figure is not to scale and is for reference only 2 B1 Max 45...

Page 82: ...telligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method as with previous generation processors supporting TM1 or TM2 The temperature a...

Page 83: ...l 0 and PROCHOT is still active then a second frequency and voltage transition will take place This sequence of temperature checking and Frequency VID reduction will continue until either the minimum...

Page 84: ...vation temperature TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio VID state 6 2 2 4 Critical Temperature Flag If TM2 is unable to reduce the processor temperat...

Page 85: ...tically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 THERMTRIP activation is independent of processor activity The temperature at which...

Page 86: ...conds over which the DTS temperature values are averaged Short averaging times will make the averaged temperature values respond more quickly to DTS changes Long averaging times will result in better...

Page 87: ...e time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action t...

Page 88: ...ge within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 2 These ratings apply to the Intel...

Page 89: ...uivalent MWAIT C state requests inside the processor and do not directly result in I O reads to the system The P_LVLx I O Monitor address does not need to be set up before using the P_LVLx I O read in...

Page 90: ...e MWAIT instruction RESET will cause the processor to initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the C1 state See the Intel 64 and IA 3...

Page 91: ...rocessor depending on the core power states and permission from the rest of the system as described in the following sections 7 2 2 1 Package C0 State This is the normal operating state for the proces...

Page 92: ...by the processor in response PM Request PMReq messages from the chipset The processor itself will never request a particular S state Notes 1 If the chipset requests an S state transition which is not...

Page 93: ...steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the VCC is ch...

Page 94: ...Features 94 Datasheet...

Page 95: ...er are dimensioned in millimeters and inches in brackets Figure 8 1 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel bo...

Page 96: ...tsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 8 2 Side View and Figure 8 3...

Page 97: ...1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Figure 8 3 Space Requirements for the Boxed Processor top view Figure 8 4 Space R...

Page 98: ...ich is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides VOH to match the system board mounted fan speed monitor requirements if appli...

Page 99: ...nto the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink...

Page 100: ...xed Processor Specifications 100 Datasheet Figure 8 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements top view Figure 8 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements side vie...

Page 101: ...y a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 40 C Meeting the processor s temperature specification see Chapter 6 is the responsibility of th...

Page 102: ...accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out...

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