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Intel CELERON PROCESSOR P4505 - ADDENDUM, Datasheet, Page: 91 / 139

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Intel CELERON PROCESSOR P4505 - ADDENDUM Datasheet Download Page 91

Intel

®

 Core

TM 

i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel

®

 Celeron

®

 Processor P4505, U3405 Series

August 2010

Datasheet Addendum

Document Number: 323178-003

91

Processor Configuration Registers

6.2.7

CL6 - Cache Line Size

B/D/F/Type:

0/6/0/PCI

Address Offset:

Ch

Default Value:

00h

Access:

RW

Size:

8 bits

6.2.8

HDR6 - Header Type

B/D/F/Type:

0/6/0/PCI

Address Offset:

Eh

Default Value:

01h

Access:

RO

Size:

8 bits

This register identifies the header layout of the configuration space. No physical 
register exists at this location.

 Regost

Table 30. CL6 - Cache Line Size Register

Bit

Access

Default 

Value

RST/

PWR

Description

7:0

RW

00h

Core

Cache Line Size (Scratch pad) 
Implemented by PCI Express devices as a read-write field for 
legacy compatibility purposes but has no impact on any PCI 
Express device functionality. 

Table 31. HDR6 - Header Type Register

Bit

Access

Default 

Value

RST/

PWR

Description

7:0

RO

01h

Core

Header Type Register (HDR) 
Returns 01 to indicate that this is a single function device with 
bridge header layout. 

Summary of Contents for CELERON PROCESSOR P4505 - ADDENDUM

Page 1: ...Document Number 323178 003 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Datasheet Addendum August 2010 ...

Page 2: ...s are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details The Intel CoreTM i7 620LE UE i7 610E and i5 520E Processor Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Curren...

Page 3: ...Express Port Bifurcation 20 3 Signal Description 21 3 1 System Memory Interface 21 3 2 Reset and Miscellaneous Signals 24 4 Electrical Specifications 25 4 1 Signal Groups 25 4 2 DC Specifications 25 4 2 1 Voltage and Current Specifications 25 5 Processor Ball and Signal Information 27 5 1 Processor Ball Assignments 27 6 Processor Configuration Registers 70 6 1 Register Terminology 70 6 1 1 DEVEN D...

Page 4: ...Vendor ID Capabilities 108 6 2 28 SS Subsystem ID and Subsystem Vendor ID 108 6 2 29 MSI_CAPID Message Signaled Interrupts Capability ID 109 6 2 30 MC Message Control 109 6 2 31 MA Message Address 111 6 2 32 MD Message Data 111 6 2 33 PEG_CAPL PCI Express G Capability List 112 6 2 34 PEG_CAP PCI Express G Capabilities 112 6 2 35 DCAP Device Capabilities 113 6 2 36 DCTL Device Control 114 6 2 37 DS...

Page 5: ... 1 Processor Documents 13 2 PCH Documents 14 3 Public Specifications 14 4 Supported DIMM Module Configurations 15 5 DDR3 System Memory Timing Support 16 6 Signal Description Buffer Types 21 7 Memory Channel A 21 8 Memory Channel B 23 9 Reset and Miscellaneous Signals 24 10 Mobile Signal Groups1 25 11 DDR3 Signal Group DC Specifications 25 12 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330...

Page 6: ...endor ID Register 108 52 MSI_CAPID Message Signaled Interrupts Capability ID Register 109 53 MC Message Control Register 109 54 MA Message Address Register 111 55 MD Message Data Register 111 56 PEG_CAPL PCI Express G Capability List Register 112 57 PEG_CAP PCI Express G Capabilities Register 112 58 DCAP Device Capabilities Register 113 59 DCTL Device Control Register 114 60 DSTS Device Status Reg...

Page 7: ...ed information for the Intel Celeron Processor P4500 and P4505 Series Corrected first bullet in Section 2 1 1 to No support for mixed ECC and non ECC DIMM configurations August 2010 003 Added information for the Intel CoreTM i7 660UE i3 330E and Celeron Processor U3405 Removed all references to Celeron Processor P4500 since it is a PGA package and does not relate to this document was included by e...

Page 8: ... 32 nanometer process technology Throughout this document Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series may be referred to as simply the processor The processor is designed for a two chip platform as opposed to the traditional three chip platforms processor GMCH and ICH The two chip platform consists of a processor and the Platform Control...

Page 9: ...TM i7 i5 i3 and Celeron Processor MCP Processor Discrete Graphics PEG Analog CRT Gigabit Network Connection USB 2 0 Intel HD Audio FWH TPM 1 2 Super I O PCI Serial ATA Mobile Intel 5 Series Chipset PCH DDR3 DIMMs PCI Express x16 14 Ports PCI 6 Ports 3 Gb s SPI Digital Display x 3 Intel Flexible Display Interface SPI Flash LPC SMBUS 2 0 PECI GPIO OR GPU Memory Controller Dual core Processor 800 106...

Page 10: ...b and 2 Gb DDR3 DRAM technologies for x8 and x16 devices Using 2 Gb device technologies the largest memory capacity possible is 8 GB assuming dual channel mode with two x8 dual rank un buffered DIMM memory configuration Up to 32 simultaneous open pages 16 per channel assuming 4 Ranks of 8 Bank Devices Memory organizations Single channel modes Dual channel modes Dual channel symmetric Interleaved D...

Page 11: ...troduction and Features Summary 1 3 Package The Intel Core i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series are available on a 34 x 28 mm BGA package BGA1288 Note Although the BGA1288 package is shared with Intel CoreTM i7 640UM LM i7 620M UM LM i5 540M i5 520M UM and i5 430M Processor Series they are not ball out compatible ...

Page 12: ...ics Processing Unit ICH The legacy I O Controller Hub component that contains the main PCI interface LPC interface USB2 Serial ATA and other I O functions It communicates with the legacy G MCH over a proprietary interconnect called DMI IMC Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the IA 32 architecture Intel FDI Intel Flexible Display Interface Intel TXT Intel T...

Page 13: ...y or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the ...

Page 14: ... Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifications PCI Express Base Specification 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com products processor manuals index htm ...

Page 15: ...rank x8 unbuffered ECC Raw Card E dual rank x8 unbuffered ECC Raw Card F dual rank x16 unbuffered non ECC DDR3 DRAM Device Technology Standard 1 Gb and 2 Gb technologies and addressing are supported for x16 and x8 devices There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other...

Page 16: ...nt configurations can exist 2 1 3 1 Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both D 512 MB 512 Mb 64 M x 8 9 1 13 10 8 8K 1 GB 1 Gb 128 M x 8 9 1 14 10 8 8K 2 GB 2 Gb 256 M x 8 9 1 15 10 8 8K E 1 GB 512 Mb 64M x 8 18 2 13 10 8 8K 2 GB 1 Gb 128...

Page 17: ...are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single ch...

Page 18: ...ector populated 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the Just in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements 2 1 5 1 Just in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most effic...

Page 19: ...y allows the IMC to further reduce latency and increase bandwidth efficiency 2 1 6 DRAM Clock Generation Two differential clock pairs for every supported DIMM There are total of four clock pairs driven directly by the processor to two DIMMs 2 1 7 DDR3 On Die Termination On Die Termination ODT is a feature that allows a DRAM device to turn on off internal termination resistance for each DQ DQS DQS ...

Page 20: ...s for the secondary port Port 1 and the associated virtual PCI to PCI bridge can be found in PCI Device 6 When the primary port is not bifurcated Device 6 is hidden from the discovery mechanism used in PCI enumeration such that configuration of the device is neither possible nor necessary Figure 4 PCI Express Related Register Structures in the Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 3...

Page 21: ...led The buffers are not 3 3 V tolerant Refer to the PCIe specification FDI Intel Flexible Display interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant DMI Direct Media Interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but are DC coup...

Page 22: ...heck data bits SA_DQ 71 64 Note Not required for non ECC mode I O DDR3 SA_DQS 7 0 Data Strobe Complements These are the complementary strobe signals I O DDR3 SA_DQ 71 64 ECC Check Data Bits SA_DQ 71 64 are the ECC check data bits for Channel A Note Not required for non ECC mode I O DDR3 SA_DQ 63 0 Data Bus Channel A data signal interface to the SDRAM data bus I O DDR3 SA_MA 15 0 Memory Address The...

Page 23: ...rential strobe pair The data is captured at the crossing point of SB_DQS 7 0 and its SB_DQS 7 0 during read and write transactions I O DDR3 SB_DQS 8 ECC Data Strobe Complement SB_DQS 8 is the complement strobe for the ECC check data bits SB_DQ 71 64 Note Not required for non ECC mode I O DDR3 SB_DQS 7 0 Data Strobe Complements These are the complementary strobe signals I O DDR3 SB_DQ 71 64 ECC Che...

Page 24: ...iguration lands A test point may be placed on the board for this land CFG 3 PCI Express Static Lane Numbering Reversal A test point may be placed on the board for this land Lane reversal will be applied across all 16 lanes 1 No Reversal 0 Reversal In the case of Bifurcation with NO Lane Reversal the physical lane mapping is as follows Lanes 15 8 Port 1 Lanes 7 0 Lanes 7 0 Port 0 Lanes 7 0 In the c...

Page 25: ...finitions The DC specifications for the DDR3 signals are listed in Table 11 4 2 1 Voltage and Current Specifications Table 10 Mobile Signal Groups1 Signal Group Alpha Group Type Signals DDR3 Data Signals2 Single ended e DDR3 Bi directional SA_DQ 71 0 SB_DQ 71 0 Differential f DDR3 Bi directional SA_DQS 8 0 SA_DQS 8 0 SB_DQS 8 0 SB_DQS 8 0 Power Ground Other Single Ended z Other DBR PROC_DETECT VCA...

Page 26: ...et 2 of 2 Symbol Parameter Alpha Group Min Typ Max Units Notes1 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 VI...

Page 27: ...y ball name for the Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series package respectively Table 13 provides a listing of all processor pins ordered alphabetically by ball number for the Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series package respectively Figure 5 Figure 6 Figure 7 and F...

Page 28: ...0 SA_BS 1 SA_CK 1 BG SB_DQ 5 8 SB_DQS 7 SA_DM 5 VSS SA_DM 4 SA_DQ 7 0 VSS BF SB_DQ 5 7 SB_DM 7 SA_DQ 6 1 SA_DQ 5 7 VSS VTT0 VTT0 SA_DQ 5 2 SA_DQ 4 8 SA_DQ 3 5 SA_DQ 3 4 SA_ODT 0 SA_MA 1 3 SA_WE BE RSVD VSS RSVD VSS SA_DQS 7 SA_DQS 7 BD SB_DQ 6 2 SB_DQ 6 3 VTT0 VTT0 VSS VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1 BC SA_DQ 6 3 SB_DQ 5 9 BB VSS RSVD SA_DQ 5 9 SA_DQ 5 8 VSS VTT0 VTT0 VSS V...

Page 29: ... 1 1 SB_DQ 7 BH SA_MA 3 SA_MA 4 SA_DQ 3 1 SA_DQ 3 0 SA_DQ 1 9 SA_DQ 2 5 SB_DQ 8 SB_DQ 9 BG VSS SA_MA 9 SA_BS 2 SA_CKE 0 VDDQ VDDQ VSS SA_DQ 9 SA_DQ 1 2 VSS SA_DQ 1 3 SB_DQ 6 BF SA_DQ 8 VSS SA_DQ 7 SA_DQ 6 SB_DQ 3 SB_DQS 0 VSS BE VDDQ SA_DQS 8 SA_DQS 8 SA_DQ 6 4 SA_DQ 6 5 SA_DQ 6 8 SB_DQ 6 5 SB_DQ 6 9 SB_DQ 6 4 SB_DQS 8 SB_DQS 8 VDDQ VSS SB_DQS 0 SB_DQ 2 BD SB_DQ 5 BC VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ...

Page 30: ...PLL P TDI_M TRST VCC N RESET_ OBS PROCH OT TMS VSS CATERR VSS VCC VSS VCC VSS VCC VSS VCC VCC PEG_TX 0 PEG_TX 1 M PROC_D ETECT BPM 7 VCC VSS VCC VCC VSS VSS L VSS VSS VCC VSS VSS PEG_TX 0 PEG_TX 1 K BCLK_IT P BPM 6 BPM 3 VSS BPM 4 VCC VSS VCC VCC VSS VSS J BCLK_IT P BPM 0 BPM 1 VSS BPM 5 BPM 2 VSS VCC VSS VSS VSS PEG_RX 1 H VSS VCC VSS VCC VCC VSS VSS G VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS PEG_...

Page 31: ...RMT RIP VSS VTT_SE NSE FDI_TX 4 FDI_TX 4 FDI_TX 1 FDI_TX 1 FDI_TX 2 N VSS PEG_RX 3 PEG_TX 2 PEG_TX 12 PEG_TX 13 PM_SYN C DMI_TX 1 FDI_TX 2 VSS M PEG_TX 8 PEG_TX 11 PEG_CL K PEG_TX 15 VSS FDI_TX 0 L VSS VSS VSS VSS PEG_RX 6 VSS DMI_TX 1 VSS DMI_RX 2 DMI_RX 2 VSS VSS FDI_TX 0 K PEG_TX 8 PEG_RX 4 PEG_CL K PEG_TX 15 DMI_TX 2 DMI_TX 3 VSS DMI_RX 1 DMI_RX 1 DMI_RX 3 DMI_RX 3 J VSS PEG_RX 2 PEG_TX 5 PEG_...

Page 32: ...F8 CMOS I CFG 16 AF6 CMOS I CFG 17 AB7 CMOS I COMP0 AE66 Analog I COMP1 AD69 Analog I COMP2 AC70 Analog I COMP3 AD71 Analog I DBR W71 O DC_TEST_A5 A5 DC_TEST_A68 A68 DC_TEST_A69 A69 DC_TEST_A71 A71 DC_TEST_BR1 BR1 DC_TEST_BR71 BR71 DC_TEST_BT1 BT1 DC_TEST_BT3 BT3 DC_TEST_BT69 BT69 DC_TEST_BT71 BT71 DC_TEST_BV1 BV1 DC_TEST_BV3 BV3 DC_TEST_BV5 BV5 DC_TEST_BV68 BV68 DC_TEST_BV69 BV69 DC_TEST_BV71 BV7...

Page 33: ...5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir PEG_CLK J21 DIFF CLK I PEG_ICOMPI B12 Analog I PEG_ICOMPO A13 Analog I PEG_RBIAS B11 Analog I PEG_RCOMPO D12 Analog I PEG_RX 0 F40 PCIe I PEG_RX 1 J38 PCIe I PEG_RX 2 G34 PCIe I PEG_RX 3 M34 PCIe I PEG_RX 4 J28 PCIe I PEG_RX 5 G25 PCIe I PEG_RX 6 K24 PCIe I PEG_RX 7 B28 PCIe I PEG_RX 8...

Page 34: ... PEG_TX 15 J20 PCIe O PM_EXT_TS 0 AV66 CMOS I PM_EXT_TS 1 AV64 CMOS I PM_SYNC M17 CMOS I PRDY U71 Async GTL O PREQ U69 Async GTL I Table 12 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir PROC_DETECT M71 PROC_DPRSLPVR F66 CMOS O PROCHOT N67 Async GTL I O PSI F68 Async CMOS O RESET_OBS N70 A...

Page 35: ...ir SA_DM 6 BN62 DDR3 O SA_DM 7 BH59 DDR3 O SA_DQ 0 AT8 DDR3 I O SA_DQ 1 AT6 DDR3 I O SA_DQ 2 BB5 DDR3 I O SA_DQ 3 BB9 DDR3 I O SA_DQ 4 AV7 DDR3 I O SA_DQ 5 AV6 DDR3 I O SA_DQ 6 BE6 DDR3 I O SA_DQ 7 BE8 DDR3 I O SA_DQ 8 BE11 DDR3 I O SA_DQ 9 BF11 DDR3 I O SA_DQ 10 BJ10 DDR3 I O SA_DQ 11 BH13 DDR3 I O SA_DQ 12 BF9 DDR3 I O SA_DQ 13 BF6 DDR3 I O SA_DQ 14 BK7 DDR3 I O SA_DQ 15 BN8 DDR3 I O SA_DQ 16 BN...

Page 36: ...el CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir SA_DQS 0 AY7 DDR3 I O SA_DQS 1 BJ5 DDR3 I O SA_DQS 2 BL13 DDR3 I O SA_DQS 3 BN21 DDR3 I O SA_DQS 4 BK44 DDR3 I O SA_DQS 5 BH51 DDR3 I O SA_DQS 6 BM60 DDR3 I O SA_DQS 7 BE64 DDR3 I O SA_DQS 8 BD33 DDR3 I O SA_DQS 0 AY5 DDR3 I O SA_DQS 1 BJ7 DDR3 I...

Page 37: ... Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir SB_DQ 16 BR10 DDR3 I O SB_DQ 17 BT12 DDR3 I O SB_DQ 18 BT15 DDR3 I O SB_DQ 19 BV15 DDR3 I O SB_DQ 20 BV12 DDR3 I O SB_DQ 21 BP12 DDR3 I O SB_DQ 22 BV17 DDR3 I O SB_DQ 23 BU16 DDR3 I O SB_DQ 24 BP15 DDR3 I O SB_DQ 25 BU19 DDR3 I O SB_DQ 26 BV22 DDR3 I O SB_DQ 27 BT22 DDR3 I O SB_DQ 28 BP19 DDR3 I O SB_DQ 29 BV19 DDR3 ...

Page 38: ...8 BD17 DDR3 I O Table 12 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir SB_MA 0 BT34 DDR3 O SB_MA 1 BP30 DDR3 O SB_MA 2 BV29 DDR3 O SB_MA 3 BU30 DDR3 O SB_MA 4 BV31 DDR3 O SB_MA 5 BT33 DDR3 O SB_MA 6 BT31 DDR3 O SB_MA 7 BP26 DDR3 O SB_MA 8 BV27 DDR3 O SB_MA 9 BT27 DDR3 O SB_MA 10 BU42 DDR3...

Page 39: ...i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VCAP0 AK57 PWR VCAP0 AL50 PWR VCAP0 AL53 PWR VCAP0 AL57 PWR VCAP0 AN50 PWR VCAP0 AN53 PWR VCAP0 AN57 PWR VCAP0 AR48 PWR VCAP0 AR51 PWR VCAP0 AR55 PWR VCAP0 AU48 PWR VCAP0 AU51 PWR VCAP0 AU55 PWR VCAP0 AW50 PWR VCAP0 AW53 PWR VCAP0 AW57 PWR VCAP0 AY50 PWR VCAP0 AY53 PWR VCAP0 AY57 PWR ...

Page 40: ...le 12 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VCC A54 REF VCC A57 REF VCC AA41 REF VCC AA44 REF VCC AA48 REF VCC AA51 REF VCC AA55 REF VCC AB41 REF VCC AB44 REF VCC AB48 REF VCC AB51 REF VCC AB55 REF VCC AD41 REF VCC AD44 REF VCC AD48 REF VCC AD51 REF VCC AD55 REF VCC AF41 REF VCC A...

Page 41: ...cessor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VCC R51 REF VCC R55 REF VCC U41 REF VCC U44 REF VCC U48 REF VCC U51 REF VCC U55 REF VCC W41 REF VCC W44 REF VCC W48 REF VCC W51 REF VCC W55 REF VCC_SENSE F64 Analog O VCCPLL R37 REF VCCPLL R39 REF VCCPLL U37 REF VCCPLL W37 REF VCCPLL W39 REF VCCPWRGOOD_0 Y67 Async CMOS I VCCPWRGOOD_1 AM7 Async CMOS I VDDQ BB15 REF VDDQ B...

Page 42: ...eTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS AA35 GND VSS AA37 GND VSS AA39 GND VSS AA4 GND VSS AA42 GND VSS AA46 GND VSS AA50 GND VSS AA53 GND VSS AA57 GND VSS AA62 GND VSS AA64 GND VSS AA66 GND VSS AB14 GND VSS AB15 GND VSS AB17 GND VSS AB19 GND VSS AB21 GND VSS AB23 GND VSS AB24 GND VSS AB...

Page 43: ...E i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS AH48 GND VSS AH50 GND VSS AH51 GND VSS AH53 GND VSS AH55 GND VSS AH57 GND VSS AH62 GND VSS AJ70 GND VSS AK15 GND VSS AK17 GND VSS AK19 GND VSS AK21 GND VSS AK23 GND VSS AK24 GND VSS AK26 GND VSS AK28 GND VSS AK30 GND VSS AK32 GND VSS AK37 GND VSS AK41 GND VSS AK44 GND VS...

Page 44: ...UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS AU15 GND VSS AU17 GND VSS AU19 GND VSS AU21 GND VSS AU23 GND VSS AU24 GND VSS AU26 GND VSS AU28 GND VSS AU30 GND VSS AU32 GND VSS AU33 GND VSS AU35 GND VSS AU39 GND VSS AU4 GND VSS AU42 GND VSS AU46 GND VSS AU50 GND VSS AU53 GND VSS AU57 GND VSS AU62 GND VSS AU70 GND VS...

Page 45: ...E i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS BB62 GND VSS BB7 GND VSS BB71 GND VSS BD14 GND VSS BD39 GND VSS BD42 GND VSS BD46 GND VSS BD50 GND VSS BD53 GND VSS BD57 GND VSS BE1 GND VSS BE65 GND VSS BE70 GND VSS BE9 GND VSS BF13 GND VSS BF30 GND VSS BF62 GND VSS BF8 GND VSS BG36 GND VSS BG51 GND VSS BH15 GND VSS BH...

Page 46: ... i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS BV66 GND VSS C68 GND VSS D10 GND VSS D13 GND VSS D17 GND VSS D20 GND VSS D24 GND VSS D27 GND VSS D31 GND VSS D34 GND VSS D38 GND VSS D41 GND VSS D6 GND VSS E12 GND VSS E16 GND VSS E30 GND VSS E33 GND VSS E37 GND VSS E5 GND VSS E68 GND VSS E69 GND VSS ...

Page 47: ... i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VSS N53 GND VSS N57 GND VSS N63 GND VSS P4 GND VSS R14 GND VSS R42 GND VSS R46 GND VSS R5 GND VSS R50 GND VSS R53 GND VSS R57 GND VSS R62 GND VSS R70 GND VSS T1 GND VSS U39 GND VSS U4 GND VSS U42 GND VSS U46 GND VSS U50 GND VSS U53 GND VSS U57 GND VSS U62 GND VSS U64 GND VSS U9 GND VSS V70 G...

Page 48: ...TM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir VTT0 AU60 REF VTT0 AW12 REF VTT0 AW14 REF VTT0 AW33 REF VTT0 AW35 REF VTT0 AW60 REF VTT0 AY10 REF VTT0 AY60 REF VTT0 BB59 REF VTT0 BB60 REF VTT0 BD59 REF VTT0 BD60 REF VTT0 BF59 REF VTT0 BF60 REF VTT0 R23 REF VTT0 R24 REF VTT0 R26 REF VTT0 R28 REF VTT0 ...

Page 49: ...0E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Name Pin Name Pin Buffer Type Dir Table 13 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir A5 DC_TEST_A5 A6 RSVD_NCTF A8 VSS GND A10 RSVD A12 VSS GND A13 PEG_ICOMPO Analog I A15 VSS GND A17 PEG_RX 14 PCIe ...

Page 50: ... UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AA69 RSVD AA71 RSVD AB2 FDI_LSYNC 1 CMOS I AB5 FDI_INT CMOS I AB7 CFG 17 CMOS I AB9 VSS GND AB12 VTT1 REF AB14 VSS GND AB15 VSS GND AB17 VSS GND AB19 VSS GND AB21 VSS GND AB23 VSS GND AB24 VSS GND AB26 VSS GND AB28 VSS GND AB30 VSS GND AB32 VSS GND AB33 VSS GND AB35 VSS ...

Page 51: ... 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AD55 VCC REF AD57 VSS GND AD59 VCAP2 PWR AD60 VCAP2 PWR AD62 VSS GND AD69 COMP1 Analog I AD71 COMP3 Analog I AE2 CFG 13 CMOS I AE64 VSS GND AE66 COMP0 Analog I AE70 VSS GND AF1 VSS GND AF4 CFG 8 CMOS I AF10 VSSAXG_SENSE Analog O AF12 VAXG_SENSE Analog O AF14 VAXG REF AF15 VAXG REF AF1...

Page 52: ...E i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AH44 VSS GND AH46 VSS GND AH48 VSS GND AH50 VSS GND AH51 VSS GND AH53 VSS GND AH55 VSS GND AH57 VSS GND AH59 VCAP2 PWR AH60 VCAP2 PWR AH62 VSS GND AH66 RSVD AH69 GFX_VR_EN CMOS O AH71 GFX_VID 3 CMOS O AJ10 VAXG REF AJ2 CFG 5 CMOS I AJ70 VSS GND AK1 CFG 2 CMOS I AK2 CFG 3 C...

Page 53: ...Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AL41 VSS GND AL42 VCAP1 PWR AL44 VSS GND AL46 VCAP1 PWR AL48 VSS GND AL50 VCAP0 PWR AL51 VSS GND AL53 VCAP0 PWR AL55 VSS GND AL57 VCAP0 PWR AL59 VTT0 REF AL60 VTT0 REF AL62 VSS GND AL69 GFX_IMON CMOS I AL71 GFX_DPRSLPVR CMOS O AM10 VTT0 REF AM2 CFG 1 CMOS I AM5 SM_DRAMPWROK Async CMOS I AM7 VCCPWRGOOD_1 Asyn...

Page 54: ... UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AR26 VSS GND AR28 VSS GND AR30 VSS GND AR32 VSS GND AR33 VSS GND AR35 VSS GND AR37 VCAP1 PWR AR39 VSS GND AR41 VCAP1 PWR AR42 VSS GND AR44 VCAP1 PWR AR46 VSS GND AR48 VCAP0 PWR AR50 VSS GND AR51 VCAP0 PWR AR53 VSS GND AR55 VCAP0 PWR AR57 VSS GND AR59 VTT0 REF AR60 VTT0 R...

Page 55: ...el Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir AW12 VTT0 REF AW14 VTT0 REF AW15 VTT0_DDR REF AW17 VTT0_DDR REF AW19 VTT0_DDR REF AW2 SB_DQ 1 DDR3 I O AW21 VTT0_DDR REF AW23 VTT0_DDR REF AW24 VTT0_DDR REF AW26 VTT0_DDR REF AW28 VTT0_DDR REF AW30 VTT0_DDR REF AW32 VTT0_DDR REF AW33 VTT0 REF AW35 VTT0 REF AW37 VSS GND AW39 VCAP1 PWR AW41 VSS GND AW42 VCA...

Page 56: ...U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir B12 PEG_ICOMPI Analog I B14 PEG_RX 15 PCIe I B16 PEG_RX 14 PCIe I B18 PEG_RX 13 PCIe I B19 PEG_RX 12 PCIe I B21 PEG_RX 11 PCIe I B23 PEG_RX 10 PCIe I B25 PEG_RX 9 PCIe I B26 PEG_RX 8 PCIe I B28 PEG_RX 7 PCIe I B30 PEG_TX 9 PCIe O B32 PEG_TX 10 PCIe O B33 PEG_TX 6 PCIe O B35 PEG_TX 7 PCIe O B37 PEG_TX 4 PCIe O B39 PEG_TX 3 PCIe O B4...

Page 57: ...4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BC70 SA_DQ 63 DDR3 I O BD1 SB_DQ 2 DDR3 I O BD4 SB_DQS 0 DDR3 I O BD14 VSS GND BD15 VDDQ REF BD17 SB_DQS 8 DDR3 I O BD19 SB_DQS 8 DDR3 I O BD21 SB_DQ 64 DDR3 I O BD23 SB_DQ 69 DDR3 I O BD24 SB_DQ 65 DDR3 I O BD26 SA_DQ 68 DDR3 I O BD28 SA_DQ 65 DDR3 I O BD30 SA_DQ 64 DDR3 I O BD32 SA_DQS 8 DDR3 I O BD33 SA_DQS 8 DDR3 I O BD35 ...

Page 58: ...i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BG17 SA_DQ 19 DDR3 I O BG24 SA_DQ 30 DDR3 I O BG25 SA_DQ 31 DDR3 I O BG32 SA_MA 4 DDR3 O BG34 SA_MA 3 DDR3 O BG36 VSS GND BG43 SA_DQ 70 DDR3 I O BG44 SA_DM 4 DDR3 O BG51 VSS GND BG53 SA_DM 5 DDR3 O BG69 SB_DQS 7 DDR3 I O BG71 SB_DQ 58 DDR3 I O BH2 SB_DQ 7 DDR3 I O BH13 SA_DQ 11 DDR3 I O BH1...

Page 59: ...O Table 13 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BK44 SA_DQS 4 DDR3 I O BK51 SA_DQS 5 DDR3 I O BK53 VSS GND BK60 VSS GND BK61 SA_DQ 55 DDR3 I O BK63 VSS GND BK64 SA_DQ 54 DDR3 I O BK67 SB_DQ 61 DDR3 I O BK70 SB_DQ 60 DDR3 I O BL1 VSS GND BL4 SB_DM 1 DDR3 O BL13 SA_DQS 2 DDR3 I O...

Page 60: ...i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BP42 VSS GND BP46 SB_CS 0 DDR3 O BP49 SB_DQ 35 DDR3 I O BP53 SB_DQ 40 DDR3 I O BP56 SB_DQ 45 DDR3 I O BP58 SA_DQS 6 DDR3 I O BP60 SB_DQ 49 DDR3 I O BR1 DC_TEST_BR1 BR3 VSS GND BR5 RSVD_NCTF BR6 SB_DQ 10 DDR3 I O BR8 SB_DQ 11 DDR3 I O BR10 SB_DQ 16 DDR3 I...

Page 61: ... i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir BU42 SB_MA 10 DDR3 O BU44 VSS GND BU46 SB_CAS DDR3 O BU48 VSS GND BU49 SB_ODT 1 DDR3 O BU51 VSS GND BU53 SB_DQ 41 DDR3 I O BU55 VSS GND BU56 SB_DQS 5 DDR3 I O BU58 VSS GND BU60 SB_DQ 46 DDR3 I O BU62 VSS GND BU63 SB_DQS 6 DDR3 I O BU65 SB_DM 6 DDR3 O BV1 DC_TEST_BV1 BV3 DC_...

Page 62: ...Ie I D27 VSS GND D29 PEG_RX 7 PCIe I Table 13 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir D31 VSS GND D33 PEG_TX 10 PCIe O D34 VSS GND D36 PEG_TX 7 PCIe O D38 VSS GND D40 PEG_TX 3 PCIe O D41 VSS GND D43 VCC REF D45 VCC REF D47 VCC REF D48 VCC REF D50 VCC REF D52 VCC REF D54 VCC REF D5...

Page 63: ...E i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir G51 VCC REF G53 VSS GND G55 VCC REF G57 VSS GND G60 VCC REF G70 VSS GND H1 VSS GND H15 VTTPWRGOOD Async CMOS I H17 DMI_TX 0 DMI O H24 PEG_RX 6 PCIe I H25 PEG_RX 5 PCIe I H32 PEG_TX 5 PCIe O H34 PEG_RX 2 PCIe I H36 VSS GND H43 VSS GND H44 VCC REF H51 VCC REF H53...

Page 64: ...LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir L47 VSS GND L48 VSS GND L55 VCC REF L57 VSS GND L70 VSS GND M1 VSS GND M4 FDI_TX 2 FDI O M15 DMI_TX 1 DMI O M17 PM_SYNC CMOS I M24 PEG_TX 13 PCIe O M25 PEG_TX 12 PCIe O M32 PEG_TX 2 PCIe O M34 PEG_RX 3 PCIe I M36 VSS GND M42 VSS GND M44 VCC REF M51 VCC REF M53 VSS GND ...

Page 65: ...61 CATERR GTL I O N63 VSS GND N65 TMS CMOS I N67 PROCHOT Async GTL I O N70 RESET_OBS Async CMOS O P1 FDI_TX 3 FDI O P4 VSS GND P34 PEG_RX 3 PCIe I P60 VCC REF P69 TRST CMOS I P71 TDI_M CMOS I R2 FDI_TX 3 FDI O R5 VSS GND R7 FDI_TX 5 FDI O R8 FDI_TX 5 FDI O R12 VSS_SENSE_VTT Analog O R14 VSS GND R15 VTT1 REF R17 VTT1 REF R19 VTT1 REF R21 VTT1 REF R23 VTT0 REF R24 VTT0 REF R26 VTT0 REF Table 13 Inte...

Page 66: ...C REF R42 VSS GND R44 VCC REF R46 VSS GND R48 VCC REF R50 VSS GND R51 VCC REF R53 VSS GND R55 VCC REF R57 VSS GND R59 VCAP2 PWR R60 VCAP2 PWR R62 VSS GND R64 RSVD R66 RSVD R70 VSS GND T1 VSS GND T2 RSVD T4 RSVD U6 FDI_TX 6 FDI O U7 FDI_TX 6 FDI O U9 VSS GND T67 TCK CMOS I T69 TDI CMOS I T70 TDO_M CMOS O T71 TDO CMOS O U1 RSVD U4 VSS GND Table 13 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3...

Page 67: ...VTT0 REF U28 VTT0 REF U30 VTT0 REF U32 VTT0 REF U33 VTT0 REF U35 VTT0 REF U37 VCCPLL REF U39 VSS GND U41 VCC REF U42 VSS GND U44 VCC REF U46 VSS GND U48 VCC REF U50 VSS GND U51 VCC REF U53 VSS GND U55 VCC REF U57 VSS GND U59 VCAP2 PWR U60 VCAP2 PWR U62 VSS GND U64 VSS GND U69 PREQ Async GTL I U71 PRDY Async GTL O V2 RSVD V70 VSS GND W1 VSS GND Table 13 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 ...

Page 68: ...F W17 VTT1 REF W19 VTT1 REF W21 VTT1 REF W23 VTT0 REF W24 VTT0 REF W26 VTT0 REF W28 VTT0 REF W30 VTT0 REF W32 VTT0 REF W33 VTT0 REF W35 VTT0 REF W37 VCCPLL REF W39 VCCPLL REF W41 VCC REF W42 VSS GND W44 VCC REF W46 VSS GND W48 VCC REF W50 VSS GND W51 VCC REF W53 VSS GND W55 VCC REF W57 VSS GND W59 VCAP2 PWR W60 VCAP2 PWR W62 VSS GND W64 RSVD W66 RSVD Table 13 Intel CoreTM i7 660UE i7 620LE UE i7 6...

Page 69: ...ument Number 323178 003 69 Processor Ball and Signal Information W69 VSS GND W71 DBR O Y2 DPLL_REF_SSCLK DIFF CLK I Y67 VCCPWRGOOD_0 Async CMOS I Y70 TAPPWRGOOD Async CMOS O Table 13 Intel CoreTM i7 660UE i7 620LE UE i7 610E i5 520E i3 330E and Intel Celeron Processor P4505 U3405 Series Ball List by Ball Number Pin Pin Name Buffer Type Dir ...

Page 70: ...a cold reset is Power Good Reset as defined in the PCI Express Base Specification AF Atomic Flag bit s The first time the bit is read with an enabled byte it returns the value 0 but a side effect of the read is that the value changes to 1 Any subsequent reads with enabled bytes return a 1 until a 1 is written to the bit When the bit is read but the byte is not enabled the state of the bit does not...

Page 71: ... this bit field from being writable bit field becomes Read Only RW V L S Read Write Volatile Lockable Sticky bit s These bits can be read and written by software Hardware may set or clear the bit based upon internal events possibly sooner than any subsequent software read could retrieve the value written Additionally there is a bit which is marked RW K or RW L K that when set prohibits this bit fi...

Page 72: ...ble Table 15 DEVEN Device Enable Register Bit Access Default Value RST PWR Description 31 15 RO 0h Reserved 14 RW L 0b Core Reserved 13 RW L 0b Core PEG1 Enable D6EN 0 Bus 0 Device 6 Function 0 is disabled and hidden 1 Bus 0 Device 6 Function 0 is enabled and visible 12 12 RO 0h Reserved 11 RW L 0b Core Reserved 10 RW L 0b Core Reserved 9 9 RO 0h Reserved 8 RW L 1b Core Reserved 7 4 RO 0h Reserved...

Page 73: ...r Software Generated Event for SMI GSGESMI This indicates the source of the SMI was a Device 2 Software Event 11 RW1C S 0b Core Processor Thermal Sensor Event for SMI SCI SERR GTSE Indicates that a Processor Thermal Sensor trip has occurred and an SMI SCI or SERR has been generated The status bit is set only if a message is sent based on thermal event enables in Error command SMI command and SCI c...

Page 74: ...rror Log register in the channel where the error occurred Once this bit is set the CxECCERRLOG fields are locked until the CPU clears this bit by writing a 1 Software uses bits 1 0 to detect whether the logged error address is for a Single bit or a Multiple bit error This bit is reset on PWROK 0 RW1C S 0b Core Single bit DRAM ECC Error Flag DSERR If this bit is set to 1 a memory read data transfer...

Page 75: ...PU lock cycle is detected that does not hit DRAM 0 Reporting of this condition via SERR messaging is disabled 8 RW 0b Core Reserved 7 RW 0b Core SERR on DRAM Throttle Condition ERR 0 Reporting of this condition via SERR messaging is disabled 1 The memory controller generates a DMI SERR special cycle when a DRAM Read or Write Throttle condition occurs 6 2 RO 00h Core Reserved 1 RW 0b Core SERR Mult...

Page 76: ...2 RO 0h Core Reserved 11 RW 0b Core SMI on Processor Thermal Sensor Trip TSTSMI 1 A SMI DMI special cycle is generated by Processor when the thermal sensor trip requires an SMI A thermal sensor trip point cannot generate more than one special cycle 0 Reporting of this condition via SMI messaging is disabled 10 2 RO 000h Core Reserved 1 RW 0b Core SMI on Multiple Bit DRAM ECC Error DMESMI 1 The Pro...

Page 77: ...Registers Bit Access Default Value RST PWR Description 23 16 RW 00h Core ECC bit invert vector C0sd_cr_eccbitinv This vector operates individually for every ECC bit in the selected 64b ECC block during write to DRAM For all k between 0 and 7 when bit k is set to 1 the value for the k ECC bit which corresponds with k data byte lane is inverted Otherwise the value for the k ECC bit is not affected 1...

Page 78: ...MERR on QW1 MERR on QW2 MERR on QW3 CERR on QW0 CERR on QW1 CERR on QW2 CERR on QW3 Table 20 Channel 0 ECC Error Registers Sheet 1 of 2 Bit Access Default Value RST PWR Description 63 48 RO P 0000h Core Error Column Address ERRCOL Row address of the address block of main memory of which an error single bit or multi bit error has occurred 47 32 RO P 0000h Core Error Row Address ERRROW Row address o...

Page 79: ...ory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors until this bit is cleared But a multiple bit error that occurs after this bit is set will over write the address error syndrome info This bit is cleared when it receives an indication that the CPU has cleared the corresponding bit in ...

Page 80: ...r have been cleared by software A multiple bit error will overwrite a single bit error Once the error flag bits are set as a result of an error this bit field is locked and doesn t change as a result of a new error until the error flag is cleared by software Same is the case with error syndrome field but the following priority needs to be followed if more than one error occurs on one or more of th...

Page 81: ...bit error has occurred 28 27 RO V S 00b Core Error Rank Address ERRRANK Rank address of the address block of main memory of which an error single bit or multi bit error has occurred 26 24 RO 000b Core Reserved 23 16 RO V S 00b Core Error Syndrome ERRSYND Syndrome that describes the set of bits associated with the first failing quadword 15 2 RO 0000h Core PReserved 1 RO V S 0b Core Multiple Bit Err...

Page 82: ...ed to first Disable the link then program the registers and then re enable the link which will cause a full retrain with the new settings Table 23 PCI Device 6 Register Sheet 1 of 3 Register Name Register Symbol Register Start Register End Default Value Access Vendor Identification VID6 0 1 8086h RO Device Identification DID6 2 3 0047h RO PCI Command PCICMD6 4 5 0000h RO RW PCI Status PCISTS6 6 7 ...

Page 83: ...01h RO Power Management Control Status PM_CS6 84 87 00000008h RO RW S RW Subsystem ID and Vendor ID Capabilities SS_CAPID 88 8B 0000800Dh RO Subsystem ID and Subsystem Vendor ID SS 8C 8F 00008086h RW O Message Signaled Interrupts Capability ID MSI_CAPID 90 91 A005h RO Message Control MC 92 93 0000h RO RW Message Address MA 94 97 00000000h RO RW Message Data MD 98 99 0000h RW PCI Express G Capabili...

Page 84: ...7 00040000h RW O RO Slot Control SLOTCTL B8 B9 0000h RO RW Slot Status SLOTSTS BA BB 0000h RO RWC Root Control RCTL BC BD 0000h RO RW Root Status RSTS C0 C3 00000000h RO RWC Link Control 2 LCTL2 D0 D1 0001h RO RW S RW Link Status 2 LSTS2 D2 D3 0000h RO PCI Express G Legacy Control PEGLC EC EF 00000000h RO RW Table 23 PCI Device 6 Register Sheet 3 of 3 Register Name Register Symbol Register Start R...

Page 85: ...ntification register uniquely identifies any PCI device Table 24 VID6 Vendor Identification Register Bit Access Default Value RST PWR Description 15 0 RO 8086h Core Vendor Identification VID6 PCI standard identification for Intel Table 25 DID6 Device Identification Register Bit Access Default Value RST PWR Description 15 4 RO 004h Core Device Identification Number DID6 UB Identifier assigned to th...

Page 86: ... 0 8 RW 0b Core SERR Message Enable SERRE1 Controls Device 6 SERR messaging The processor communicates the SERR condition by sending an SERR message to the PCH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Reg...

Page 87: ...pt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus Upstream memory writes reads IO writes reads peer writes reads and MSIs will all be treated as illegal cycles Writes are forwarded to memory address C0000h with byte enables deasserted Reads is forwarded to m...

Page 88: ...d to 0 The concept of a master abort does not exist on primary side of this device 12 RO 0b Core Received Target Abort Status RTAS Not Applicable or Implemented Hard wired to 0 The concept of a target abort does not exist on primary side of this device 11 RO 0b Core Signaled Target Abort Status STAS Not Applicable or Implemented Hard wired to 0 The concept of a target abort does not exist on prima...

Page 89: ...at a capabilities list is present Hard wired to 1 3 RO 0b Core INTA Status INTAS Indicates that an interrupt message is pending internally to the device Only PME and Hot Plug sources feed into this status bit not PCI INTA INTD assert and deassert messages The INTA Assertion Disable bit PCICMD6 10 has no effect on this bit Note that INTA emulation interrupts received across the link are not reflect...

Page 90: ...specific programming interface Table 28 RID6 Revision Identification Register Bit Access Default Value RST PWR Description 7 0 RO 10h Core Revision Identification Number RID6 This is an 8 bit value that indicates the revision identification number for the processor Device 0 For the C 0 Stepping this value is 10h Table 29 CC6 Class Code Register Bit Access Default Value RST PWR Description 23 16 RO...

Page 91: ...s This register identifies the header layout of the configuration space No physical register exists at this location Regost Table 30 CL6 Cache Line Size Register Bit Access Default Value RST PWR Description 7 0 RW 00h Core Cache Line Size Scratch pad Implemented by PCI Express devices as a read write field for legacy compatibility purposes but has no impact on any PCI Express device functionality ...

Page 92: ... the second bus side of the virtual bridge i e to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G Table 32 PBUSN6 Primary Bus Number Register Bit Access Default Value RST PWR Description 7 0 RO 00h Core Primary Bus Number BUSN Configuration software typically programs this field with the number of the bus on the pr...

Page 93: ...0 PCI Address Offset 1Ch Default Value F0h Access RO RW Size 8 bits This register controls the CPU to PCI Express G I O access routing based on the following formula IO_BASE address IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined I O address range is aligned to a 4 KB boundary Table 34 SUBUSN6 Subordi...

Page 94: ...e defined I O address range is at the top of a 4 KB aligned address block Table 35 IOBASE6 I O Base Address Register Bit Access Default Value RST PWR Description 7 4 RW Fh Core I O Address Base IOBASE Corresponds to A 15 12 of the I O addresses passed by bridge 1 to PCI Express G BIOS must not set this register to 00h otherwise 0CF8h 0CFCh accesses is forwarded to the PCI Express hierarchy associa...

Page 95: ...ved Master Abort RMA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status 12 RWC 0b Core Received Target Abort RTA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header D...

Page 96: ...T The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range is align...

Page 97: ...nd MLIMIT registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the p...

Page 98: ...bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range is aligned to a 1 MB boundary Table 40 PMBASE6 ...

Page 99: ...d to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range is at the top of a 1 MB aligned memory block Note Prefetchable memory range is supported to allow segregation by the configuration software between the memory r...

Page 100: ...ng formula PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address ...

Page 101: ...pond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range is at the top of a 1 MB alig...

Page 102: ...ting information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information Table 44 CAPPTR6 Capabilities Pointer Register Bit Access Default Value RST PWR Description 7 0 RO 88h Core First Capability CAPPTR6 The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability Table 45 INTRLINE...

Page 103: ...anges mapping Table 46 INTRPIN6 Interrupt Pin Register Bit Access Default Value RST PWR Description 7 0 RO 01h Core Interrupt Pin INTPIN As a single function device the PCI Express device specifies INTA as its interrupt pin 01h INTA Table 47 BCTRL6 Bridge Control Register Sheet 1 of 2 Bit Access Default Value RST PWR Description 15 12 RO 0h Core Reserved 11 RO 0b Core Discard Timer SERR Enable DTS...

Page 104: ...sponse by the processor to an I O access issued by the CPU that target ISA I O addresses This applies only to I O addresses that are enabled by the IOBASE and IOLIMIT registers 0 All addresses defined by the IOBASE and IOLIMIT for CPU I O transactions is mapped to PCI Express G 1 Processor will not forward to PCI Express G any I O transactions addressing the last 768 bytes in each 1 KB block even ...

Page 105: ...o 0 to indicate that the D1 power management state is NOT supported 24 22 RO 000b Core Auxiliary Current AUXC hard wired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements 21 RO 0b Core Device Specific Initialization DSI hard wired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it 20 RO 0b Core Auxilia...

Page 106: ...ement data register 8 RW S 0b Core PME Enable PMEE Indicates that this device does not generate PMEB assertion from any D state 0 PMEB generation not possible from any D State 1 PMEB generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 4 RO 0000b Core Reserved 3 RO 1b Core No Soft Reset NSR When set to 1 this bit indicates that the device is tran...

Page 107: ... does not require any special action While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the D0 state in order to be fully functional When the Power State is other than D0 the bridge will Master Abort i e not claim...

Page 108: ... can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset Table 50 SS_CAPID Subsystem ID and Vendor ID Capabilities Register Bit Access Default Value RST PWR Description 31 16 RO 0000h Core Reserved 15 8 RO 80h Core Pointer to Next Capability PNC This contains a pointer to the next item in the capabilitie...

Page 109: ...t the device is prohibited from doing so If the device writes the same message multiple times only one of those messages is guaranteed to be serviced If all of them must be serviced the device must not generate the same message again until the driver services the earlier one Table 52 MSI_CAPID Message Signaled Interrupts Capability ID Register Bit Access Default Value RST PWR Description 15 8 RO A...

Page 110: ... MMC field below 3 1 RO 000b Core Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device Value Number of Messages Requested 000 1 All of the following are reserved in this implementation 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved 0 RW 0b Core MSI Enable MSIEN Controls the ability of this device to generate MSI...

Page 111: ...age Address MA Used by system software to assign an MSI address to the device The device handles an MSI by writing the padded contents of the MD register to this address 1 0 RO 00b Core Force DWord Align FDWA hard wired to 0 so that addresses assigned by system software are always aligned on a dword address boundary Table 55 MD Message Data Register Bit Access Default Value RST PWR Description 15 ...

Page 112: ...y other PCI Express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space 7 0 RO 10h Core Capability ID CID Identifies this linked list item capability structure as being for PCI Express registers Table 57 PEG_CAP PCI Express G Capabilities Register Bit Access Default Value RST PWR Description...

Page 113: ...ess Default Value RST PWR Description Table 58 DCAP Device Capabilities Register Bit Access Default Value RST PWR Description 31 16 RO 0000h Core Reserved Not Applicable or Implemented Hard wired to 0 15 RO 1b Core Role Based Error Reporting RBER Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express Base spec 14 6 RO 000h Core Res...

Page 114: ...RO 0b Core Reserved Reserved for Extended Tag Field Enable 7 5 RW 000b Core Max Payload Size MPS 000 128B max supported payload for Transaction Layer Packets TLP As a receiver the Device must handle TLPs as large as the set value as transmitter the Device must not generate TLPs exceeding the set value All other encodings are reserved Hardware will actually ignore this field It is writeable only to...

Page 115: ...trol the full scope of related error reporting Table 59 DCTL Device Control Register Sheet 2 of 2 Bit Access Default Value RST PWR Description Table 60 DSTS Device Status Register Bit Access Default Value RST PWR Description 15 6 RO 000h Core Reserved and Zero RSVD For future R WC S implementations software must use 0 for writes to bits 5 RO 0b Core Transactions Pending TP 0 All pending transactio...

Page 116: ...tal error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register 0 RWC 0b Core Correctable Error Detected CED When set this bit indicates that correctable error s were detect...

Page 117: ...of the Slot Capabilities register this bit must be set to 1b For Upstream Ports and components that do not support this optional capability this bit must be hard wired to 0b 19 RO 0b Core Surprise Down Error Reporting Capable SDERC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition For Upstre...

Page 118: ...ediate and undesired value from ever existing 14 12 RO 100b Core L0s Exit Latency L0SELAT Indicates the length of time this Port requires to complete the transition from L0s to L0 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to less than 1 µs 101 1 µs to less than 2 µs 110 2 µs 4 µs 111 More than 4 µs The actual value of...

Page 119: ...ables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches 9 RW 0b Core Hardware Autonomous Width Disable HAWD When Set this bit disables hardware from changing the Link width for reasons other than attempting to correct un...

Page 120: ...t and the component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the L0s Exit Latency reported in LCAP 14 12 and the N_FTS value advertised during link training 5 RW SC 0b Core Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer LTSSM from L0 L0s or L1 states to the Recovery...

Page 121: ...n that Link When disabling ASPM L1 software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1 Table 62 LCTL Link Control Register Sheet 3 of 3 Bit Access Default Value RST PWR Description Table 63 LSTS Link Status Register ...

Page 122: ... This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hard wired to 0b 12 RO 1b Core Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the presence of a reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connector 11 RO 0b Core...

Page 123: ...ue RST PWR Description 31 19 RW O 0000h Core Physical Slot Number PSN Indicates the physical slot number attached to this Port BIOS Requirement This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis 18 RW O 1b Core No Command Completed Support NCCS When set to 1b this bit indicates that this slot does not generate software notificati...

Page 124: ...otification This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation 4 RO 0b Core Reserved for Power Indicator Present PIP When set to 1b this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot 3 RO 0b Core Reserved for Attention Indicator Present AI...

Page 125: ...lete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to the slot or within the adapter Note that in some cases the power controller may autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the ...

Page 126: ...o be read only with a value of 0b 4 RO 0b Core Reserved for Command Completed Interrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 1b this bit enables software notification when a hot plug command is completed by the Hot Plug Controller Default value of this field is 0b If Command Completed ...

Page 127: ...ot plugged device 7 RO 0b Core Reserved for Electromechanical Interlock Status EIS If an Electromechanical Interlock is implemented this bit indicates the current status of the Electromechanical Interlock Defined encodings are 0b Electromechanical Interlock Disengaged 1b Electromechanical Interlock Engaged 6 RO 0b Core Presence Detect State PDS In band presence detect state 0b Slot Empty 1b Card p...

Page 128: ...is bit must be hard wired to 0b 3 RWC 0b Core Presence Detect Changed PDC A pulse indication that the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is changed 2 RO 0b Core Reserved for MRL Sensor Changed MSC If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected If an MRL sensor is not implemented this ...

Page 129: ...pts are generated as a result of receiving PME messages 1 Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state 2 RW 0b Core System Error on Fatal Error Enable SEFEE 0 Controls the Root Complex s res...

Page 130: ...e R WC S implementations software must use 0 for writes to bits 17 RO 0b Core PME Pending PMEP Indicates that another PME is pending when the PME Status bit is set When the PME Status bit is cleared by software the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately The PME pending bit is cleared by hardware if no more PMEs are pending 16 RW...

Page 131: ...n 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is of type RsvdP The default value of this bit is 0b Components that support only the 2 5 GT s speed are permitted to hardwire this field to 0b 10 RW S 0b Core Enter Modified Compliance entermodcompliance When this bit is set to 1b the device transmits modified compliance pa...

Page 132: ...ated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link 3 0 RW 1h Core Target Link Speed TLS For Downstream ports this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences Defined encodings are 0001b 2 5Gb s Target Link Speed All oth...

Page 133: ...TS2 Link Status 2 Register Sheet 2 of 2 Table 71 PEGLC PCI Express G Legacy Control Register Bit Access Default Value RST PWR Description 31 3 RO 00000000h Core Reserved 2 RW 0b Core PME GPE Enable PMEGPE 0 Do not generate GPE PME message when PME is received 1 Generate a GPE PME message when PME is received This enables the processor to support PMEs on the PEG port under legacy OSs 1 RW 0b Core H...

Page 134: ...Register End Default Value Access Virtual Channel Enhanced Capability Header VCECH 100 103 00010002h RW O RO Port VC Capability Register 1 PVCCAP1 104 107 00000000h RO Port VC Capability Register 2 PVCCAP2 108 10B 00000000h RO Port VC Control PVCCTL 10C 10D 0000h RO RW VC0 Resource Capability VC0RCAP 110 113 00000001h RO VC0 Resource Control VC0RCTL 114 117 800000FFh RO RW VC0 Resource Status VC0R...

Page 135: ...apability Register 1 Bit Access Default Value RST PWR Description 31 12 RO 00000h Core Reserved 11 10 RO 00b Core Reserved Reserved for Port Arbitration Table Entry Size 9 8 RO 00b Core Reserved Reserved for Reference Clock 7 RO 0b Core Reserved 6 4 RO 000b Core Low Priority Extended VC Count LPEVCC Indicates the number of extended Virtual Channels in addition to the default VC belonging to the lo...

Page 136: ...annel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO 0000h Core Reserved 7 0 RO 00h Core Reserved for VC Arbitration Capability VCAC Table 76 PVCCTL Port VC Control Bit Access Default Value RST PWR Description 15 4 RO 000h Core Reserved 3 1 RW 000b Core VC Arbitration Select VCAS This field is programmed by software to the only possible v...

Page 137: ...es types of Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic Each bit location within this field corresponds to a Port Arbitration Capability defined below When more than one bit in this field is Set it indic...

Page 138: ...ar Port Arbitration service This field is valid for RCRBs Root Ports that support peer to peer traffic and Switch Ports but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 RO 0b Core Reserved Reserved fo...

Page 139: ...omplete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel so...

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