Datasheet, Volume 1
85
Electrical Specifications
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The V
CCIO
referred to in these specifications refers to instantaneous V
CCIO
.
3.
For V
IN
between “0” V and V
CCIO
. Measured when the driver is tristated.
4.
V
IH
and V
OH
may experience excursions above
V
CCIO. However, input signal drivers must comply with the
signal quality specifications.
Notes:
1.
Refer to the PCI Express Base Specification for more details.
2.
V
TX-AC-CM-PP
and V
TX-AC-CM-P
are defined in the PCI Express Base Specification. Measurement is made over
at least 10^
6
UI.
3.
As measured with compliance test load. Defined as 2*|V
TXD+
– V
TXD-
|.
4.
COMP resistance must be provided on the system board with 1% resistors.
5.
PEG_ICOMPO, PEG_COMPI, PEG_RCOMPO are the same resistor.
6.
RMS value.
7.
Measured at Rx pins into a pair of 50-
Ω
terminations into ground. Common mode peak voltage is defined by
the expression: max{|(Vd+ - Vd-) - V-CMDC|}.
8.
DC impedance limits are needed to ensure Receiver detect.
9.
The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to
ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately
and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50
Ω
±20%) must be within the
specified range by the time Detect is entered.
10. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
11. These are pre-silicon estimates and are subject to change.
Table 7-9.
Control Sideband and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Units
Notes
1
V
IL
Input Low Voltage
—
V
CCIO
* 0.3
V
2
V
IH
Input High Voltage
V
CCIO
* 0.7
—
V
2, 4
V
OL
Output Low Voltage
—
V
CCIO
* 0.1
V
2
V
OH
Output High Voltage
V
CCIO
* 0.9
—
V
2, 4
R
ON
Buffer on Resistance
23
73
Ω
I
LI
Input Leakage Current
—
±200
μ
A
3
Table 7-10. PCI Express* DC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
1,11
V
TX-DIFF-p-p Low
Low differential peak to peak Tx voltage
swing
0.4
0.5
0.6
V
3
V
TX-DIFF-p-p
Differential peak to peak Tx voltage swing
0.8
1
1.2
V
3
V
TX_CM-AC-p
Tx AC Peak Common Mode Output
Voltage (Gen1 only)
—
—
20
mV
1, 2, 6
V
TX_CM-AC-p-p
Tx AC Peak Common Mode Output
Voltage (Gen2 only)
—
—
100
mV
1, 2
Z
TX-DIFF-DC
DC Differential Tx Impedance (Gen1 only)
80
90
120
Ω
1, 10
Z
RX-DC
DC Common Mode Rx Impedance
40
45
60
Ω
1, 8, 9
Z
RX-DIFF-DC
DC Differential Rx Impedance (Gen1 only)
80
90
120
Ω
1
V
RX-DIFFp-p
Differential Rx input Peak to Peak Voltage
(Gen1 only)
0.175
—
1.2
V
1
V
RX-DIFFp-p
Differential Rx input Peak to Peak Voltage
(Gen2 only)
0.12
—
1.2
V
1
V
RX_CM-AC-p
Rx AC peak Common Mode Input Voltage
150
—
—
mV
1, 7
PEG_ICOMPO
Comp Resistance
24.75
25
25.25
Ω
4, 5
PEG_COMPI
Comp Resistance
24.75
25
25.25
Ω
4, 5
PEG_RCOMPO
Comp Resistance
24.75
25
25.25
Ω
4, 5
Summary of Contents for BX80623I32100
Page 34: ...Interfaces 34 Datasheet Volume 1...
Page 42: ...Technologies 42 Datasheet Volume 1...
Page 58: ...Power Management 58 Datasheet Volume 1...
Page 60: ...Thermal Management 60 Datasheet Volume 1...
Page 70: ...Signal Description 70 Datasheet Volume 1...
Page 88: ...Electrical Specifications 88 Datasheet Volume 1...
Page 108: ...Processor Pin and Signal Information 108 Datasheet Volume 1...